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RM0453 Rev 1 87/1461

RM0453 Global security controller (GTZC)

3.5.4 GTZC TZSC unprivileged watermark 1 register

(GTZC_TZSC_MPCWM1_UPWMR)

Address offset: 0x130

Reset value: 0x0FFF 0000

Privileged write access only.

This register can be written only by secure privileged transaction, when the corresponding

Flash user option FSD is configured as secure. If non-secure, this register can be written by

secure privileged and non-secure privileged transaction.

Read access is authorized for any type of transaction, secure/non-secure,

privileged/unprivileged.

When TZSC configuration is locked in GTZC_TZSC_CR.LCK, this register cannot be

modified.

Note: When the system is non-secure (ESE = 0), this register can be written and read, however

bits have no function.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. LGTH[11:0]

rw rw rw rw rw rw rw rw rw rw rw rw

1514131211109876543210

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

Bits 31:28 Reserved, must be kept at reset value.

Bits 27:16 LGTH[11:0]: Define the length of user Flash unprivileged area (in 2-Kbyte resolution, starting

from the user Flash base address)

Note: This register has only effect when security is enabled (ESE = 1). When security is

disabled, the memory is completely unprivileged, whatever the value.

0x000: No unprivileged area, privileged 0x00000 to 0x3FFFF

0x001: Unprivileged 0x00000 to 0x007FF, privileged 0x00800 to 0x3FFFF

0x002: Unprivileged 0x00000 to 0x00FFF, privileged 0x01000 to 0x3FFFF

0x003: Unprivileged 0x00000 to 0x017FF, privileged 0x01800 to 0x3FFFF

.....

0x080 and greater: Unprivileged 0x00000 to 0x3FFFF, no privileged area

Note: 0x800 and greater are truncated to 0x800.

Bits 15:0 Reserved, must be kept at reset value.

ST STM32WL5 Series User Manual

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