RM0453 Rev 1 889/1461
RM0453 General-purpose timer (TIM2)
901
26.4.10 TIM2 capture/compare mode register 2 [alternate] (TIM2_CCMR2)
Address offset: 0x1C
Reset value: 0x0000 0000
The same register can be used for output compare mode (this section) or for input capture
mode (previous section). The direction of a channel is defined by configuring the
corresponding CCxS bits. All the other bits of this register have a different function in input
and in output mode.
Output compare mode:
Bits 9:8 CC4S[1:0]: Capture/Compare 4 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC4 channel is configured as output
01: CC4 channel is configured as input, IC4 is mapped on TI4
10: CC4 channel is configured as input, IC4 is mapped on TI3
11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if
an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER).
Bits 7:4 IC3F[3:0]: Input capture 3 filter
Bits 3:2 IC3PSC[1:0]: Input capture 3 prescaler
Bits 1:0 CC3S[1:0]: Capture/Compare 3 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC3 channel is configured as output
01: CC3 channel is configured as input, IC3 is mapped on TI3
10: CC3 channel is configured as input, IC3 is mapped on TI4
11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if
an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER).
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res.
OC4M
[3]
Res. Res. Res. Res. Res. Res. Res.
OC3M
[3]
rw rw
1514131211109876543210
OC4CE OC4M[2:0] OC4PE OC4FE CC4S[1:0] OC3CE OC3M[2:0] OC3PE OC3FE CC3S[1:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:25 Reserved, must be kept at reset value.
Bits 23:17 Reserved, must be kept at reset value.
Bit 15 OC4CE: Output compare 4 clear enable
Bits 24, 14:12 OC4M[3:0]: Output compare 4 mode
Refer to OC1M description (bits 6:4 in TIMx_CCMR1 register)
Bit 11 OC4PE: Output compare 4 preload enable
Bit 10 OC4FE: Output compare 4 fast enable
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