Advanced-control timer (TIM1) RM0453
824/1461 RM0453 Rev 1
Note: Refer to Figure 150: TIM1 ETR input circuitry and to Figure 171: Break and Break2 circuitry
overview.
25.4.28 TIM1 Alternate function register 2 (TIM1_AF2)
Address offset: 0x64
Reset value: 0x0000 0001
Bit 2 BKCMP2E: BRK COMP2 enable
This bit enables the COMP2 for the timer’s BRK input. COMP2 output is ‘ORed’ with the
other BRK sources.
0: COMP2 input disabled
1: COMP2 input enabled
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
in TIMx_BDTR register).
Bit 1 BKCMP1E: BRK COMP1 enable
This bit enables the COMP1 for the timer’s BRK input. COMP1 output is ‘ORed’ with the
other BRK sources.
0: COMP1 input disabled
1: COMP1 input enabled
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
in TIMx_BDTR register).
Bit 0 BKINE: BRK BKIN input enable
This bit enables the BKIN alternate function input for the timer’s BRK input. BKIN input is
‘ORed’ with the other BRK sources.
0: BKIN input disabled
1: BKIN input enabled
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
in TIMx_BDTR register).
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res.
BK2
CMP2
P
BK2
CMP1
P
BK2
INP
Res. Res. Res. Res. Res. Res.
BK2
CMP2E
BK2
CMP1E
BK2INE
rw rw rw rw rw rw
Bits 31:12 Reserved, must be kept at reset value.
Bit 11 BK2CMP2P: BRK2 COMP2 input polarity
This bit selects the COMP2 input sensitivity. It must be programmed together with the BK2P
polarity bit.
0: COMP2 input polarity is not inverted (active low if BK2P=0, active high if BK2P=1)
1: COMP2 input polarity is inverted (active high if BK2P=0, active low if BK2P=1)
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
in TIMx_BDTR register).
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