RM0453 Rev 1 499/1461
RM0453 Nested vectored interrupt controller (NVIC)
505
15 Nested vectored interrupt controller (NVIC)
15.1 NVIC main features
CPU1 NVIC features:
• 62 maskable interrupt channels (not including the sixteen Cortex-M4 with DSP interrupt
lines)
• 16 programmable priority levels (four bits of interrupt priority used)
• Low-latency exception interrupt handling
• Power management control
• Implementation of system control registers
CPU2 NVIC features:
• 32 maskable interrupt channels (not including the sixteen Cortex
®
-M0+ interrupt lines)
• Four programmable priority levels (two bits of interrupt priority used)
• Low-latency exception interrupt handling
• Power management control
The NVICs and the processor cores interfaces are closely coupled, resulting in low-latency
interrupt processing and efficient processing of late arriving interrupts.
All interrupts including the core exceptions are managed by the NVIC.
For more information on exceptions and NVIC programming, refer to the PM0214
programming manual for Cortex
®
-M4 (PM0214), and programming manual for
Cortex
®
-M0+ (PM0223).
15.2 Interrupt block diagram
The different peripheral interrupts are connected in different ways, depending on the sharing
between the two CPUs.
To prevent a peripheral or EXTI interrupt to trigger both CPUs, they can be masked either in
the NVIC, or, for the NVIC vector sharing multiple peripheral interrupts, by a pre-mask in the
SYSCFG registers (see Section 11: System configuration controller (SYSCFG)).
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