ST STM32WL5 Series User Manual

RM0453 Rev 1 511/1461
RM0453 Extended interrupts and event controller (EXTI)
524
16.4.1 EXTI configurable event input wakeup
The extended interrupt/event block diagram for configurable events is shown in Figure 55.
The configurable events allow the system and CPU wakeup from Sleep and Stop modes,
and provide a pending flag in the EXTI.
Figure 55. Configurable event trigger logic CPU wakeup
The software interrupt event register allows configurable events to be triggered by software,
writing the corresponding register bit, irrespective of the edge selection setting.
The rising and falling edges selection registers allow the configurable event active trigger
edge (or both edges) to be enabled.
The CPU has its dedicated interrupt mask and event mask registers. The enabled event
allows the generation of an event on the CPU. All events for a CPU are ORed together into
a single CPU event signal. The event pending register (EXTI_PR) is not set for an
unmasked CPU event.
The configurable events have unique interrupt pending request registers, shared by the
CPU. The pending register is only set for an unmasked interrupt. Each configurable event
provides a common interrupt to the CPU. The configurable event interrupts need to be
acknowledged by software in the EXTI_PR register.
When a CPU interrupt or CPU event is enabled, the asynchronous edge detection circuit is
reset by the clocked delay and rising edge detect pulse generator. This guarantees that the
EXTI hclk clock is woken up before the asynchronous edge detection circuit is reset.
Note: A detected configurable event interrupt pending request may be cleared by the CPU. The
system is not able to enter into low-power modes as long as an interrupt pending request is
active.
16.4.2 EXTI direct event input wakeup
The extended interrupt/event block diagram for direct events is shown in Figure 56. The
direct events allow the wakeup of the system and of the CPU from Sleep and Stop modes.
1. Only for input events with configuration “rxev generation” enabled.
MSv60760V1
EVG
Rising edge
detect
Asynchronous edge
detection circuit
EXTI
Peripheral interface
Configurable
event
input(y)
it_exti_per(y)
CPUn event(y)
(1)
cn_wakeup
rst
hclk
hclk
sys_wakeup
Other wakeups
CPUn
other events(x,y)
cn_event
Logic duplicated for each CPU
hclk
AHB
interface
Other CPUn
Imask(y)
ck_fclk_cn
hclk
rst
cn_evt_exti
cn_evt_rst
Same circuit for configurable
and direct events
Falling
trigger
selection
register
Rising
trigger
selection
register
Software
interrupt
event
register
CPUn
event
mask
register
CPUn
interrupt
mask
register
Pending
request
register
Rising
edge
detect
pulse
generator
Delay
CPUn
other wakeups
CPUn
wakeup(y)
Synch
CPUn rising
edge detect
pulse
generator
1) Only for the input events supporting the CPUn rxrev generation cn_event.

ST STM32WL5 Series Specifications

General

Brand	ST
Model	STM32WL5 Series
Category	Microcontrollers
Language	English