RM0453 Rev 1 387/1461
RM0453 Inter-processor communication controller (IPCC)
392
9.4.2 IPCC processor 1 mask register (IPCC_C1MR)
Address offset: 0x004
Reset value: 0xFFFF FFFF
Bits 31:17 Reserved, must be kept at reset value.
Bit 16 TXFIE: Processor 1 transmit channel free interrupt enable
Associated with IPCC_C1TOC2SR.
1: Enable an unmasked processor 1 transmit channel free to generate a TX free interrupt.
0: Processor 1 TX free interrupt disabled
Bits 15:1 Reserved, must be kept at reset value.
Bit 0 RXOIE: Processor 1 receive channel occupied interrupt enable
Associated with IPCC_C2TOC1SR.
1: Enable an unmasked processor 1 receive channel occupied to generate an RX occupied
interrupt.
0: Processor 1 RX occupied interrupt disabled
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
CH6
FM
CH5
FM
CH4
FM
CH3
FM
CH2
FM
CH1
FM
rw rw rw rw rw rw
15141312111098765 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
CH6
OM
CH5
OM
CH4
OM
CH3
OM
CH2
OM
CH1
OM
rw rw rw rw rw rw
Bits 31:22 Reserved, must be kept at reset value.
Bits 21:16 CHnFM: Processor 1 transmit channel n status set, (n = 6 to 1).
Associated with IPCC_C1TOC2SR.CHnF
1: Transmit channel n free interrupt masked.
0: Transmit channel n free interrupt not masked.
Bits 15:6 Reserved, must be kept at reset value.
Bits 5:0 CHnOM: Processor 1 receive channel n status clear (n = 6 to 1).
Associated with IPCC_C2TOC1SR.CHnF
1: Receive channel n occupied interrupt masked.
0: Receive channel n occupied interrupt not masked.
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