Power control (PWR) RM0453
224/1461 RM0453 Rev 1
Backup domain access
After a system reset, the Backup domain (RTC and TAMP backup registers) is protected
against possible unwanted write accesses. The DBP bit must be set in the PWR control
register 1 (PWR_CR1) to enable access to the Backup domain
VBAT battery charging
When V
DD
is present, It is possible to charge the external battery on VBAT through an
internal resistance.
The VBAT charging is done either through a 5 kΩ resistor or through a 1.5 kΩ resistor,
depending on the VBRS bit value in the PWR control register 4 (PWR_CR4).
The battery charging is enabled by setting VBE bit in the PWR control register 4
(PWR_CR4), and automatically disabled in VBAT mode.
6.1.3 Voltage regulator
Two embedded linear voltage regulators supply all the digital circuitries, except for the
Standby circuitry and the Backup domain. The main regulator (MR) output voltage (V
CORE
)
can be programmed by software to two different power ranges (range 1 and range 2) to
optimize the consumption depending on the system maximum operating frequency (refer to
Section 7.2.9: Clock source frequency versus voltage scaling and to Section 4.3.4: Read
access latency.
The voltage regulators are always enabled after a reset. Depending on the application
modes, the V
CORE
supply is provided either by the main regulator or by the low-power
regulator (LPR), as detailed below:
• In Run, Sleep and Stop 0 modes, both regulators are enabled and the main regulator
(MR) supplies full power to the V
CORE
domain (core, memories and digital peripherals).
• In LPRun and LPSleep modes, the main regulator (MR) is off and the low-power
regulator (LPR) supplies reduced power to the V
CORE
domain, preserving the contents
of the registers and internal SRAM1 and SRAM2.
• In Stop 1 and Stop 2 modes, the main regulator (MR) is off and the low-power regulator
(LPR) supplies low power to the all or part of the V
CORE
domain, preserving the
contents of all or part of the registers and of internal SRAM1 and SRAM2.
• In Standby modes with SRAM2 content preserved (RRS bit set in the PWR control
register 3 (PWR_CR3)), the main regulator (MR) is off and the low-power regulator
(LPR) provides the supply to SRAM2 only. The core and digital peripherals (except
Standby circuitry and Backup domain), SRAM1 is powered off.
• In Standby mode, both regulators (MR and LPR) are powered off. The contents of the
registers and of SRAM1 and SRAM2 is lost except for the Standby circuitry and the
Backup domain.
• In Shutdown mode, both regulators are powered off. When exiting from Shutdown
mode, a power-on reset is generated. Consequently, the contents of the registers and
of both SRAM1 and SRAM2 is lost, except for the Backup domain.
6.1.4 Dynamic voltage scaling management
The dynamic voltage scaling is a power management technique that consists in increasing
or decreasing the voltage used for the digital peripherals (V
CORE
), according to the
application performance and power consumption needs.
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