ST STM32WL5 Series - Figure 139. Counter Timing Diagram, Internal Clock Divided by 4; Figure 140. Counter Timing Diagram, Internal Clock Divided by N

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Advanced-control timer (TIM1) RM0453

740/1461 RM0453 Rev 1

Figure 139. Counter timing diagram, internal clock divided by 4

Figure 140. Counter timing diagram, internal clock divided by N

0000

0001

0000

MS31186V1

CK_PSC

Timerclock = CK_CNT

Counter register

Update event (UEV)

Counter underflow

Update interrupt flag

(UIF)

CNT_EN

001F20

MS31187V1