ST STM32WL5 Series

RM0453 Rev 1 1303/1461
RM0453 Serial peripheral interface / integrated interchip sound (SPI/I2S)
1323
Figure 380. Start sequence in master mode
In slave mode, the way the frame synchronization is detected, depends on the value of
ASTRTEN bit.
If ASTRTEN = 0, when the audio interface is enabled (I2SE = 1), then the hardware waits for
the appropriate transition on the incoming WS signal, using the CK signal.
MSv37520V2
dum: not significant data
WS (O)
SD (O)
CK (O),
CKPOL = 0
Left sample Right sample
I2SE
WS (O)
CK (O),
CKPOL = 1
SD (O)
Left sample Right sample
WS (O)
SD (O)
Sample1 Sample 2
Master I2S Philips Standard
Master I2S MSB or LSB justified
Master PCM short frame
I2SE
I2SE
CK (O),
CKPOL = 0
CK (O),
CKPOL = 1
CK (O), CKPOL = 0
CK (O),
CKPOL = 1
dum
dum
dum
I2SE
WS (O)
SD (O)
Sample1 Sample 2
Master PCM long frame
CK (O),
CKPOL = 0
CK (O), CKPOL = 1
dum