ST STM32WL5 Series User Manual

Debug support (DBG) RM0453
1412/1461 RM0453 Rev 1
38.11.9 TPIU claim tag clear register (TPIU_CLAIMCLR)
Address offset: 0xFA4
Reset value: 0x0000 0000
38.11.10 TPIU device configuration register (TPIU_DEVIDR)
Address offset: 0xFC8
Reset value: 0x0000 0CA0
Bits 31:4 Reserved, must be kept at reset value.
Bits 3:0 CLAIMSET[3:0]: sets claim tag bits
Write:
0000: No effect
xxx1: Sets bit 0.
xx1x: Sets bit 1.
x1xx: Sets bit 2.
1xxx: Sets bit 3.
Read:
0xF: Indicates there are four bits in claim tag.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CLAIMCLR[3:0]
rw rw rw rw
Bits 31:4 Reserved, must be kept at reset value.
Bits 3:0 CLAIMCLR[3:0]: resets claim tag bits
Write:
0000: No effect
xxx1: Clears bit 0.
xx1x: Clears bit 1.
x1xx: Clears bit 2.
1xxx: Clears bit 3.
Read: Returns current value of claim tag.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res.
SWON
RZ
SWOM
AN
TCLKD
ATA
FIFOSIZE[2:0]
CLKRE
LAT
MAXNUM[4:0]
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ST STM32WL5 Series Specifications

General

Brand	ST
Model	STM32WL5 Series
Category	Microcontrollers
Language	English