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Inter-integrated circuit (I2C) interface RM0453

1090/1461 RM0453 Rev 1

Figure 297. Transfer bus diagrams for I2C master receiver

MS19865V1

Example I2C master receiver 2 bytes, automatic end mode (STOP)

INIT: program Slave address, program NBYTES = 2, AUTOEND=1, set START

EV1: RXNE ISR: rd data1

EV2: RXNE ISR: rd data2

RXNE RXNE

NBYTES

legend:

transmission

reception

SCL stretch

EV1

xx 2

INIT

Example I2C master receiver 2 bytes, software end mode (RESTART)

INIT: program Slave address, program NBYTES = 2, AUTOEND=0, set START

EV1: RXNE ISR: rd data1

EV2: RXNE ISR: read data2

EV3: TC ISR: program Slave address, program NBYTES = N, set START

RXNE RXNE

NBYTES

legend:

transmission

reception

SCL stretch

EV1 EV2

INIT

EV2

AddressS A data1 data2 NA ReS Address

S Address

data1

data2

NA P

Default Chapter1
- Sub-Ghz Radio Generic Synchronization Word Control Register1
- Table of Contents2
- Sub-Ghz Radio Generic Synchronization Word Control Register2
- SYSCFG External Interrupt Configuration Register3
Documentation Conventions58
- General Information58
- List of Abbreviations for Registers58
- Glossary59
- Availability of Peripherals59
Memory and Bus Architecture60
- System Architecture60
- Boot Configuration62
- Table 1. Device Boot Mode62
- CPU2 Boot64
- SRAM Erase65
- Memory Protection65
- Table 2. SRAM Erase Conditions65
- Figure 2. Memory Protection Example67
- Table 3. Memory Security and Privilege Access68
- Memory Organization70
Global Security Controller (GTZC)77
- GTZC Introduction77
- GTZC Main Features77
- GTZC Security System Architecture77
- GTZC Functional Description78
- GTZC TZSC Registers84
- GTZC TZIC Registers92
Embedded Flash Memory (FLASH)97
- FLASH Introduction97
- FLASH Main Features97
- FLASH Functional Description97
- FLASH Option Bytes112
- Secure System Memory116
  - Introduction116
  - RSSLIB Functions116
- Flash Memory Protection117
- FLASH Program Erase Suspension125
- FLASH Interrupts126
  - Illegal Access Interrupts126
  - Table 23. Flash Interrupt Requests126
- Register Access Protection127
- FLASH Registers128
Sub-Ghz Radio (SUBGHZ)154
- Sub-Ghz Radio Introduction154
- Sub-Ghz Radio Main Features154
- Sub-Ghz Radio Functional Description155
- Sub-Ghz Radio Clocks159
- Sub-Ghz Radio Modems160
- Sub-Ghz Radio Data Buffer168
- Sub-Ghz Radio Operating Modes169
- Sub-Ghz Radio SPI Interface174
- Sub-Ghz Radio Application Configuration205
- Sub-Ghz Radio Registers207
Power Control (PWR)219
- Power Supplies219
- Power Supply Supervisor225
- Radio Busy Management228
- Figure 22. EOL Thresholds228
- Figure 23. Radio Busy Management229
- CPU2 Boot230
- Figure 24. CPU2 Boot Options231
- Low-Power Modes232
- PWR Registers254
Reset and Clock Control (RCC)277
- Reset277
- Clocks279
- Low-Power Modes296
- Table 62. Low-Power Debug Configurations296
- RCC Registers298
Hardware Semaphore (HSEM)365
- Introduction365
- Main Features365
- Functional Description366
- HSEM Registers372
Inter-Processor Communication Controller (IPCC)379
- IPCC Introduction379
- IPCC Main Features379
- IPCC Functional Description379
- IPCC Registers386
General-Purpose I/Os (GPIO)393
- GPIO Introduction393
- GPIO Main Features393
- GPIO Functional Description393
- GPIO Registers402
System Configuration Controller (SYSCFG)428
- SYSCFG Main Features428
- SYSCFG Registers428
Peripherals Interconnect Matrix446
- Introduction446
- Connection Summary446
- Table 76. Stm32Wl5X Peripherals Interconnect Matrix446
- Interconnection Details447
Direct Memory Access Controller (DMA)454
- Introduction454
- DMA Main Features454
- DMA Implementation455
- DMA Functional Description456
- DMA Interrupts466
- DMA Registers466
DMA Request Multiplexer (DMAMUX)480
- Introduction480
- DMAMUX Main Features481
- DMAMUX Implementation481
- DMAMUX Functional Description484
- DMAMUX Interrupts490
- Table 87. DMAMUX Interrupts490
- DMAMUX Registers492
Nested Vectored Interrupt Controller (NVIC)499
- NVIC Main Features499
- Interrupt Block Diagram499
- Interrupt and Exception Vectors500
- Table 89. CPU1 Vector Table500
- Figure 53. Interrupt Block Diagram500
- Table 90. CPU2 Vector Table503
Extended Interrupts and Event Controller (EXTI)506
- EXTI Main Features506
- EXTI Block Diagram506
- Table 91. EXTI Pin Overview507
- Table 92. EVG Pin Overview507
- Figure 54. EXTI Block Diagram507
- EXTI Connections between Peripherals and CPU508
  - EXTI Wakeup Interrupt List508
  - Table 93. Wakeup Interrupts508
- EXTI Functional Description510
- EXTI Functional Behavior512
- Table 95. Masking Functionality512
- Figure 56. Direct Event Trigger Logic CPU Wakeup512
- EXTI Registers513
Cyclic Redundancy Check Calculation Unit (CRC)525
- Introduction525
- CRC Main Features525
- CRC Functional Description526
- CRC Registers528
Analog-To-Digital Converter (ADC)532
- Introduction532
- ADC Main Features533
- ADC Functional Description534
- Conversion on External Trigger and Trigger Polarity (EXTSEL, EXTEN)547
- Data Management552
- Low-Power Features555
- Analog Window Watchdog (AWD1EN, AWD1SGL, AWD1CH, Adc_Awdxcr, Adc_Awdxtr)558
- Oversampler562
- Temperature Sensor and Internal Reference Voltage565
- Figure 83. Triggered Oversampling Mode (TOVS Bit = 1)565
- Figure 84. Temperature Sensor and VREFINT Channel Block Diagram566
- Battery Voltage Monitoring567
- ADC Interrupts568
- Table 109. ADC Interrupts568
- Figure 85. VBAT Channel Block Diagram568
- ADC Registers570
- ADC Register Map591
- Table 110. ADC Register Map and Reset Values591
Digital-To-Analog Converter (DAC)593
- Introduction593
- DAC Main Features593
- DAC Implementation594
- Table 111. DAC Features594
- DAC Functional Description595
- DAC Low-Power Modes606
- Table 117. Effect of Low-Power Modes on DAC606
- DAC Interrupts607
- Table 118. DAC Interrupts607
- DAC Registers608
Voltage Reference Buffer (VREFBUF)619
- Introduction619
- VREFBUF Functional Description619
- Table 120. VREF Buffer Modes619
- VREFBUF Registers620
Comparator (COMP)622
- COMP Introduction622
- COMP Main Features622
- COMP Functional Description623
- COMP Low-Power Modes628
- COMP Interrupts628
- Table 126. Comparator Behavior in the Low-Power Modes628
- Table 127. Interrupt Control Bits628
- COMP Registers629
True Random Number Generator (RNG)634
- Introduction634
- RNG Main Features634
- RNG Functional Description635
- RNG Interrupts642
- RNG Processing Time643
- RNG Entropy Source Validation643
- RNG Registers645
AES Hardware Accelerator (AES)650
- Introduction650
- AES Main Features650
- AES Implementation651
- AES Functional Description651
- AES Interrupts685
- AES Processing Latency686
- Table 139. AES Interrupt Requests686
- Table 140. Processing Latency for ECB, CBC and CTR686
- Table 141. Processing Latency for GCM and CCM (in Clock Cycles)686
- AES Registers687
Public Key Accelerator (PKA)699
- Introduction699
- PKA Main Features699
- PKA Functional Description699
- PKA Operating Modes705
- Example of Configurations and Processing Times717
- PKA Interrupts724
- Table 171. ECDSA Verification Average Computation Times724
- Table 172. Point on Elliptic Curve Fp Check Average Computation Times724
- Table 173. Montgomery Parameters Average Computation Times724
- Table 174. PKA Interrupt Requests724
- PKA Registers725
Advanced-Control Timer (TIM1)729
- TIM1 Introduction729
- TIM1 Main Features730
- Figure 128. Advanced-Control Timer Block Diagram731
- TIM1 Functional Description732
- TIM1 Registers790
General-Purpose Timer (TIM2)830
- TIM2 Introduction830
- TIM2 Main Features830
- Figure 188. General-Purpose Timer Block Diagram831
- TIM2 Functional Description832
- TIM2 Registers874
General-Purpose Timers (TIM16/TIM17)902
- TIM16/TIM17 Introduction902
- TIM16/TIM17 Main Features902
- Figure 237. TIM16/TIM17 Block Diagram903
- TIM16/TIM17 Functional Description904
- TIM16/TIM17 Registers930
Low-Power Timer (LPTIM)953
- Introduction953
- LPTIM Main Features953
- LPTIM Implementation954
- LPTIM Functional Description954
- LPTIM Low-Power Modes968
- LPTIM Interrupts968
- Table 201. Effect of Low-Power Modes on the LPTIM968
- Table 202. Interrupt Events968
- LPTIM Registers969
Infrared Interface (IRTIM)982
- Figure 269. IRTIM Internal Hardware Connections with TIM16 and TIM17982
Independent Watchdog (IWDG)983
- Introduction983
- IWDG Main Features983
- IWDG Functional Description983
- IWDG Registers986
System Window Watchdog (WWDG)992
- Introduction992
- WWDG Main Features992
- WWDG Functional Description992
- WWDG Interrupts995
- WWDG Registers995
Real-Time Clock (RTC)998
- Introduction998
- RTC Main Features998
- RTC Functional Description999
- RTC Low-Power Modes1016
- Table 212. Effect of Low-Power Modes on RTC1016
- Table 213. RTC Pins Functionality over Modes1016
- RTC Interrupts1017
- Table 214. Interrupt Requests1017
- RTC Registers1018
Tamper and Backup Registers (TAMP)1041
- Introduction1041
- TAMP Main Features1041
- TAMP Functional Description1042
- TAMP Low-Power Modes1046
- TAMP Interrupts1046
- Table 219. Effect of Low-Power Modes on TAMP1046
- Table 220. Interrupt Requests1046
- TAMP Registers1047
Inter-Integrated Circuit (I2C) Interface1058
- Introduction1058
- I2C Main Features1058
- I2C Implementation1059
- I2C Functional Description1059
- I2C Low-Power Modes1108
- Table 236. Effect of Low-Power Modes on the I2C1108
- I2C Interrupts1109
- Table 237. I2C Interrupt Requests1109
- I2C Registers1110
Universal Synchronous/Asynchronous Receiver1127
Transmitter (USART/UART)1127
- USART Introduction1127
- USART Main Features1128
- USART Extended Features1129
- USART Implementation1129
- Table 239. USART / LPUART Features1129
- USART Functional Description1130
- USART in Low-Power Modes1176
- Table 244. Effect of Low-Power Modes on the USART1176
- USART Interrupts1177
- Table 245. USART Interrupt Requests1177
- USART Registers1178
Low-Power Universal Asynchronous Receiver1214
Transmitter (LPUART)1214
- LPUART Introduction1214
- LPUART Main Features1215
- LPUART Implementation1216
- Table 247. USART / LPUART Features1216
- LPUART Functional Description1217
- LPUART in Low-Power Modes1240
- Table 252. Effect of Low-Power Modes on the LPUART1240
- LPUART Interrupts1241
- Table 253. LPUART Interrupt Requests1241
- LPUART Registers1242
Serial Peripheral Interface / Integrated Interchip Sound (SPI/I2S)1267
- Introduction1267
- SPI Main Features1267
- I2S Main Features1268
- SPI/I2S Implementation1268
- Table 255. Stm32Wl5X SPI and SPI/I2S Implementation1268
- SPI Functional Description1269
- SPI Interrupts1293
- Table 256. SPI Interrupt Requests1293
- I2S Functional Description1294
- I2S Interrupts1312
- Table 258. I2S Interrupt Requests1312
- SPI and I2S Registers1313
Debug Support (DBG)1324
- DBG Introduction and Main Features1324
- DBG Use Cases1325
- DBG Functional Description1325
- Debug Port (DP) Registers1332
- Access Ports1342
- Data Watchpoint and Trace Unit (DWT)1350
- Cross Trigger Interface (CTI) and Cross Trigger Matrix (CTM)1364
- CPU1 ROM Table1384
- CPU1 Breakpoint Unit (FPB)1392
- CPU1 Instrumentation Trace Macrocell (ITM)1399
- CPU1 Trace Port Interface Unit (TPIU)1407
- Microcontroller Debug Unit (DBGMCU)1420
- CPU2 ROM Tables1427
- CPU2 Breakpoint Unit (BPU)1440
Device Electronic Signature1449
- Device Electronic Signature Registers1449
Revision History1453
- Table 288. Document Revision History1453

Brand	ST
Model	STM32WL5 Series
Category	Microcontrollers
Language	English

ST STM32WL5 Series User Manual

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