Low-power universal asynchronous receiver transmitter (LPUART) RM0453
1222/1461 RM0453 Rev 1
– When FIFO mode is enabled, this indicates that both TXFIFO and shift register are
empty.
This check is required to avoid corrupting the last transmission when the LPUART is
disabled or enters Halt mode.
Single byte communication
• When FIFO mode disabled:
Writing to the transmit data register always clears the TXE bit. The TXE flag is set by
hardware to indicate that:
– the data have been moved from the LPUART_TDR register to the shift register
and data transmission has started;
– the LPUART_TDR register is empty;
– the next data can be written to the LPUART_TDR register without overwriting the
previous data.
The TXE flag generates an interrupt if the TXEIE bit is set.
When a transmission is ongoing, a write instruction to the LPUART_TDR register
stores the data in the TDR register, which is copied to the shift register at the end of the
current transmission.
When no transmission is ongoing, a write instruction to the LPUART_TDR register
places the data in the shift register, the data transmission starts, and the TXE bit is set.
• When FIFO mode is enabled, the TXFNF (TXFIFO Not Full) flag is set by hardware to
indicate that:
– the TXFIFO is not full;
– the LPUART_TDR register is empty;
– the next data can be written to the LPUART_TDR register without overwriting the
previous data. When a transmission is ongoing, a write operation to the
LPUART_TDR register stores the data in the TXFIFO. Data are copied from the
TXFIFO to the shift register at the end of the current transmission.
When the TXFIFO is not full, the TXFNF flag stays at ‘1’ even after a write in
LPUART_TDR. It is cleared when the TXFIFO is full. This flag generates an interrupt if
TXFNEIE bit is set.
Alternatively, interrupts can be generated and data can be written to the TXFIFO when
the TXFIFO threshold is reached. In this case, the CPU can write a block of data
defined by the programmed threshold.
If a frame is transmitted (after the stop bit) and the TXE flag (TXFE is case of FIFO
mode) is set, the TC bit goes high. An interrupt is generated if the TCIE bit is set in the
LPUART_CR1 register.
After writing the last data in the LPUART_TDR register, it is mandatory to wait for
TC = 1 before disabling the LPUART or causing the device to enter the low-power
mode (see Figure 335: TC/TXE behavior when transmitting).
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