RM0453 Rev 1 605/1461
RM0453 Digital-to-analog converter (DAC)
618
In addition, when V
DD
is removed (example the device enters in STANDBY or VBAT modes)
the calibration is required.
The steps to perform a user trimming calibration are as below:
1. If the DAC channel is active, write 0 to EN1 bit in DAC_CR to disable the channel.
2. Select a mode where the buffer is enabled, by writing to DAC_MCR register,
MODE1[2:0] = 000b or 001b or 100b or 101b.
3. Start the DAC channel calibration, by setting the CEN1 bit in DAC_CR register to 1.
4. Apply a trimming algorithm:
a) Write a code into OTRIM1[4:0] bits, starting by 00000b.
b) Wait for t
TRIM
delay.
c) Check if CAL_FLAG1 bit in DAC_SR is set to 1.
d) If CAL_FLAG1 is set to 1, the OTRIM1[4:0] trimming code is found and can be
used during device operation to compensate the output value, else increment
OTRIM1[4:0] and repeat sub-steps from (a) to (d) again.
The software algorithm may use either a successive approximation or dichotomy techniques
to compute and set the content of OTRIM1[4:0] bits in a faster way.
The commutation/toggle of CAL_FLAG1 bit indicates that the offset is correctly
compensated and the corresponding trim code must be kept in the OTRIM1[4:0] bits in
DAC_CCR register.
Note: A t
TRIM
delay must be respected between the write to the OTRIM1[4:0] bits and the read of
the CAL_FLAG1 bit in DAC_SR register in order to get a correct value.This parameter is
specified into datasheet electrical characteristics section.
If V
DDA
, VREF+ and temperature conditions do not change during device operation while it
enters more often in standby and VBAT mode, the software may store the OTRIM1[4:0] bits
found in the first user calibration in the flash or in back-up registers. then to load/write them
directly when the device power is back again thus avoiding to wait for a new calibration time.
When CEN1 bit is set, it is not allowed to set EN1 bit.
19.4.13 DAC channel conversion modes
Four conversion modes are possible.
Independent trigger without wave generation
To configure the DAC in this conversion mode, the following sequence is required:
1. Set the DAC channel trigger enable bit, TEN1.
2. Configure the trigger sources by setting different values in the TSEL1[3:0] bits.
3. Load the DAC channel data into the desired DHR register (DAC_DHR12RD,
DAC_DHR12LD or DAC_DHR8RD).
When a DAC channel trigger arrives, the DHR1 register is transferred into DAC_DOR1
(three dac_pclk clock cycles later).
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