Debug support (DBG) RM0453
1430/1461 RM0453 Rev 1
38.13.2 CPU2 ROM1 CoreSight peripheral identity register 4
(C2ROM1_PIDR4)
Address offset: 0xFD0
Reset value: 0x0000 0004
38.13.3 CPU2 ROM1 CoreSight peripheral identity register 0
(C2ROM1_PIDR0)
Address offset: 0xFE0
Reset value: 0x0000 00C0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. F4KCOUNT[3:0] JEP106CON[3:0]
rrrrrrrr
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:4 F4KCOUNT[3:0]: register file size
0x0: Register file occupies a single 4-Kbyte region
Bits 3:0 JEP106CON[3:0]: JEP106 continuation code
0x4: Arm
®
JEDEC continuation code
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. PARTNUM[7:0]
rrrrrrrr
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 PARTNUM[7:0]: part number bits [7:0]
0xC0: Cortex
®
-M0+ processor ROM table
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