RM0453 Rev 1 897/1461
RM0453 General-purpose timer (TIM2)
901
26.4.22 TIM2 option register 1 (TIM2_OR1)
Address offset: 0x50
Reset value: 0x0000 0000
26.4.23 TIM2 alternate function option register 1 (TIM2_AF1)
Address offset: 0x60
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TI4_RMP[1:0]
ETR_
RMP
Res.
rw rw rw
Bits 31:4 Reserved, must be kept at reset value.
Bits 3:2 TI4_RMP[1:0]: Timer input 4 remap
Set and cleared by software.
00: TIM2 TI4 is connected to GPIO: Refer to Alternate Function mapping
01: TIM2 TI4 is connected to COMP1_OUT
10: TIM2 TI4 is connected to COMP2_OUT
11: TIM2 TI4 is connected to a logical OR between COMP1_OUT and COMP2_OUT
Bit 1 ETR_RMP: External trigger 1 remap
Set and cleared by software.
0: TIM2 ETR is connected to GPIO: Refer to Alternate Function mapping
1: LSE internal clock is connected to TIM2_ETR input
Bit 0 Reserved, must be kept at reset value.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ETRSEL[3:2]
rw rw
1514131211109876543210
ETRSEL[1:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
rw rw
Bits 31:18 Reserved, must be kept at reset value.
Bits 17:14 ETRSEL[3:0]: ETR source selection
These bits select the ETR input source.
0000: GPIO or LSE internal clock, as per ETR_RMP bit in TIM2_OR1
0001: COMP1
0010: COMP2
Others: Reserved
Bits 13:0 Reserved, must be kept at reset value.
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