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Reset and clock control (RCC) RM0453

322/1461 RM0453 Rev 1

7.4.19 RCC APB1 peripheral clock enable register 2 (RCC_APB1ENR2)

Address offset: 0x05C

Reset value: 0x0000 0000

Access: no wait state, word, half-word and byte access

Note: When the peripheral clock is not active, the peripheral registers read or write access from

CPU1 is not supported.

Bit 14 SPI2S2EN: CPU1 SPI2S2 clock enable

This bit is set and cleared by software.

0: SPI2S2 clock disabled for CPU1

1: SPI2S2 clock enabled for CPU1

Bits 13:12 Reserved, must be kept at reset value.

Bit 11 WWDGEN: CPU1 Window watchdog clock enable

This bit is set by software to enable the window watchdog clock. It is reset by hardware

system reset. This bit is forced to 1 by hardware when the hardware WWDG_SW option is

reset.

0: Window watchdog clock disabled for CPU1

1: Window watchdog clock enabled for CPU1

Bit 10 RTCAPBEN: CPU1 RTC APB bus clock enable

This bit is set and cleared by software.

RTC kernel clock is controlled by RCC_BDCR register bit RTCEN bit.

0: RTC APB bus clock disabled for CPU1

1: RTC APB bus clock enabled for CPU1

Bits 9:1 Reserved, must be kept at reset value.

Bit 0 TIM2EN: CPU1 timer 2 clock enable

This bit is set and cleared by software.

0: TIM2 clock disabled for CPU1

1: TIM2 clock enabled for CPU1

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

1514131211109876543210

Res. Res. Res. Res. Res. Res. Res. Res. Res.

LPTIM3EN

LPTIM2EN

Res. Res. Res. Res.

LPUART1EN

rw rw rw

ST STM32WL5 Series User Manual

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