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Reset and clock control (RCC) RM0453

356/1461 RM0453 Rev 1

7.4.46 RCC CPU2 APB3 peripheral clock enable in Sleep mode register

(RCC_C2APB3SMENR)

Address offset: 0x184

Reset value: 0x0000 0001

Access: word, half-word and byte access

Bit 10 Reserved, must be kept at reset value.

Bit 9 ADCSMEN: ADC clocks enable during CPU2 CSleep and CStop modes

This bit is set and cleared by software.

0: ADC bus clock disabled by the clock gating during CPU2 CSleep and CStop modes

1: ADC bus clock enabled by the clock gating during CPU2 CSleep mode, disabled during

CPU2 CStop mode

Bits 8:0 Reserved, must be kept at reset value.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

1514131211109876543210

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

SUBG

HZSPI

SMEN

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 SUBGHZSPISMEN: sub-GHz radio SPI clock enable during CPU2 CSleep and CStop modes

This bit is set and cleared by software.

0: Sub-GHz radio SPI clock disabled by the clock gating during CPU2 CSleep and CStop

modes

1: Sub-GHz radio SPI clock enabled by the clock gating during CPU2 CSleep mode,

disabled during CPU2 CStop mode

ST STM32WL5 Series User Manual

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