ST STM32WL5 Series User Manual

RM0453 Rev 1 137/1461
RM0453 Embedded Flash memory (FLASH)
153
Bit 31 C2BOOT_LOCK: CPU2 boot lock enable option bit
This bit may be set by software at any time but a write to clear is only taken into account in
one of the following conditions:
- when ESE = 0 and staying in RDP level 0
- when ESE = 1 and staying in RDP level 0 by regressing FSD
- when ESE = 0 and regressing RDP level from 1 to 0
- when ESE = 1 and regressing RDP level from 1 to 0 and regressing ESE and or FSD.
0: CPU2 boot lock disabled
1: CPU2 boot lock enabled
Bit 30 BOOT_LOCK: CPU1 boot lock enable option bit
This bit may be set by software at any time, but a write to clear is only taken into account in
one of the following conditions:
- when staying in RDP level 0
- when regressing RDP level from 1 to 0
0: CPU1 boot lock disabled
1: CPU1 boot lock enabled
Bits 29:28 Reserved, must be kept at reset value.
Bit 27 nBOOT0: nBOOT0 option bit
If nSWBOOT0 bit selects BOOT0 to be taken from option bit nBOOT0, then this bit,
together with option nBOOT1, selects the boot modes (from the user Flash memory,
SRAM1 or system Flash memory). Refer to Section 2.2: Boot configuration.
0: nBOOT0=0
1: nBOOT0=1
Bit 26 nSWBOOT0: software BOOT0 selection
0: BOOT0 taken from the option bit nBOOT0
1: BOOT0 taken from PH3/BOOT0 pin
Bit 25 SRAM_RST: SRAM1 and SRAM2 erase when system reset
0: SRAM1 and SRAM2 erased when a system reset occurs
1: SRAM1 and SRAM2 not erased when a system reset occurs
Note: PKA SRAM is always erased on any system.
Bit 24 SRAM2_PE: SRAM2 parity check enable
0: SRAM2 parity check enabled
1: SRAM2 parity check disable
Bit 23 nBOOT1: boot configuration
Together with the BOOT0 pin or option bit nBOOT0 (depending on nSWBOOT0 option bit
configuration), this bit selects boot mode from the user Flash memory, SRAM1 or system
Flash memory. Refer to Section 2.2: Boot configuration.
Bits 22:20 Reserved, must be kept at reset value.
Bit 19 WWDG_SW: window watchdog selection
0: Hardware window watchdog
1: Software window watchdog
Bit 18 IWDG_STDBY: independent watchdog counter freeze in Standby mode
0: Independent watchdog counter frozen in Standby mode
1: Independent watchdog counter running in Standby mode

ST STM32WL5 Series Specifications

General

Brand	ST
Model	STM32WL5 Series
Category	Microcontrollers
Language	English