RM0453 Rev 1 249/1461
RM0453 Power control (PWR)
276
SRAM1, SRAM2, PWR, Flash memory interface, RCC, GTZC TZSC, GTZC TZIC, EXTI,
IPCC, IWDG, WWDG, GPIO, CRC, SYSCFG, RTC and TAMP contents and registers in the
Backup domain are also preserved. The content of all other peripherals is reset and must be
reprogrammed.
The BOR is always available in Stop 2 mode. The consumption is increased when
thresholds higher than V
BOR0
are used.
The BOR and PDR can be activated to sample periodically the supply voltage. This option
enabled by setting the ULPEN bit of the PWR_CR3 register allows the current consumption
to be decreased in this mode, but any drop of the voltage below the operating conditions
between two active periods of the supply detector, results in a non-generation of PDR reset.
Note: The comparators, LPUART1 and LPTIM1 outputs are forced to low speed
(OSPEEDy
= 0b00) during the Standby mode.
I/O states in Stop 2 mode
In Stop 2 mode, all I/O pins keep the same state as in the Run mode.
Enter Stop 2 mode
The Stop 2 mode is entered as described in Section 6.5.3, when the SLEEPDEEP bit in the
Cortex system control register is set (see Table 53).
Stop 2 mode can only be entered from Run mode. It is not possible to enter Stop 2 mode
from the LPRun mode.
If Flash memory programming is ongoing, the Stop 2 mode entry is delayed until the
memory access is finished.
If an access to the APB domain is ongoing, The Stop 2 mode entry is delayed until the APB
access is finished.
Several peripherals can be used in Stop 2 mode and can add consumption if they are
enabled and clocked by LSI or LSE: LPTIM1, I2C3 and LPUART1.
In Stop 2 mode, when HSIKERON is enabled, the wakeup capabilities of some peripherals
are also available when clocked by HSI16: I2C3 or LPUART1.
The comparators can be used in Stop 2 mode, PVM3 and PVD as well. If they are not
needed, they must be disabled by software to save their power consumption.
ADC, temperature sensor and VREFBUF buffer can consume power during Stop 2 mode,
unless they are disabled before entering this mode.
All the peripherals that cannot be used in Stop 2 mode are powered down.
Exit Stop 2 mode
The Stop 2 mode is exited according Section 6.5.4 (see Table 53).
When exiting Stop 2 mode by issuing an interrupt or a wakeup event, the HSI16 oscillator is
selected as system clock if the bit STOPWUCK is set in RCC clock configuration register
(RCC_CFGR). The MSI oscillator is selected as system clock if the bit STOPWUCK is
cleared. The wakeup time is shorter when HSI16 is selected as wakeup system clock. The
MSI selection allows a wakeup at higher frequency, up to 48 MHz,
The STOP2F status flag in the PWR control register 3 (PWR_CR3) indicates that the MCU
was in Stop 2 mode. All non retained registers are reset after wakeup from Stop 2. When
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