Direct memory access controller (DMA) RM0453
460/1461 RM0453 Rev 1
When a channel x is configured in secure mode, the following access controls rules are
applied:
• A non-secure read access to a register field of this channel is forced to return 0, except
for both the secure state and the privileged state of this channel x (SECM and PRIV
bits of the DMA_CCRx register) which are readable by a non-secure software.
• A non-secure write access to a register field of this channel has no impact.
When a channel is configured in secure mode, a secure software can separately configure
as secure or non-secure the AHB DMA master transfer from the source (by the
DMA_CCRx.SSEC register bit), and as secure or non-secure the AHB DMA master transfer
to the destination (by the DMA_CCRx.DSEC register bit).
The DMA controller generates a secure bus, dma_secm[7:0], reflecting the
DMA_CCRx.SECM register, in order to keep the other hardware peripherals like the
DMAMUX, informed of the secure/non-secure state of each DMA channel x.
The DMA controller also generates a security illegal access pulse event, dma_ilac, on an
illegal non-secure software access to a secure DMA register or register field.
A security illegal access event is generated in the configurations described below:
• If the channel x is in secure state (SECM bit of the DMA_CCRx register set), a security
illegal access is generated on one of the following accesses:
– a non-secure write access to a dedicated register of this channel x (DMA_CCRx,
DMA_CNDTRx, DMA_CPARx, DMA_CM0ARx and DMA_CM1ARx)
– a non-secure read access to a dedicated register of this channel x, except the
DMA_CxCR register (DMA_CNDTRx, DMA_CPARx, DMA_CM0ARx, and
DMA_CM1ARx).
• If the channel x is in non-secure state (SECM bit of the DMA_CCRx register cleared), a
security illegal access is generated on a non-secure write access to the DMA_CCRx
register which attempts to write 1 into any of the secure configuration bits SECM,
DSEC, SSEC.
When the software is switching from a secure state to a non-secure state (after the secure
transfer is completed), the secure software must disable the channel by a 32-bit write at the
DMA_CCRx address before switching. This operation is needed for the two below reasons:
• a non-secure software cannot do so
• the EN bit of the DMA_CCRx register must be cleared before the (non-secure)
software can reprogram the DMA_CCRx for a next transfer.
Note: A trusted application may require that the secure software does not only disable the
channel, but also reset the full DMA_CCRx word register to its reset value, as well as reset
any other DMA register corresponding to this channel x.
Privileged / unprivileged mode
Any channel x is a privileged or unprivileged hardware resource, as configured by a
privileged software via the PRIV bit of the DMA_CCRx register.
When a channel x is configured in privileged mode, the following access controls rules are
applied:
• An unprivileged read access to a register field of this channel is forced to return 0,
except for both the privileged state and the secure state of this channel x (PRIV and
SECM bits of the DMA_CCRx register) which are readable by an unprivileged software.
• An unprivileged write access to a register field of this channel has no impact.
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