RM0453 Rev 1 803/1461
RM0453 Advanced-control timer (TIM1)
829
corresponding CCxS bits. All the other bits of this register have a different function for input
capture and for output compare modes. It is possible to combine both modes independently
(e.g. channel 1 in input capture mode and channel 2 in output compare mode).
Output compare mode:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. OC2M[3] Res. Res. Res. Res. Res. Res. Res. OC1M[3]
rw rw
1514131211109 8 7654321 0
OC2
CE
OC2M[2:0]
OC2
PE
OC2
FE
CC2S[1:0]
OC1
CE
OC1M[2:0]
OC1
PE
OC1
FE
CC1S[1:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:25 Reserved, must be kept at reset value.
Bits 23:17 Reserved, must be kept at reset value.
Bit 15 OC2CE: Output Compare 2 clear enable
Refer to OC1CE description.
Bits 24, 14:12 OC2M[3:0]: Output Compare 2 mode
Refer to OC1M[3:0] description.
Bit 11 OC2PE: Output Compare 2 preload enable
Refer to OC1PE description.
Bit 10 OC2FE: Output Compare 2 fast enable
Refer to OC1FE description.
Bits 9:8 CC2S[1:0]: Capture/Compare 2 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC2 channel is configured as output
01: CC2 channel is configured as input, IC2 is mapped on TI2
10: CC2 channel is configured as input, IC2 is mapped on TI1
11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if
an internal trigger input is selected through the TS bit (TIMx_SMCR register)
Note: CC2S bits are writable only when the channel is OFF (CC2E = ‘0’ in TIMx_CCER).
Bit 7 OC1CE: Output Compare 1 clear enable
0: OC1Ref is not affected by the ocref_clr_int signal
1: OC1Ref is cleared as soon as a High level is detected on ocref_clr_int signal
(OCREF_CLR input or ETRF input)
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