CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4)
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(2) Operation of event counter mode
(1) During the operation stop state (TEmn=0), the timer count register mn (TCRmn) maintains the
initial value.
(2) Enter the operating enabled state (TEmn=1) by writing 1 to the TSmn bit.
(3) Load the value of the timer data register mn (TDRmn) into the TCRmn register while both the
TSmn bit and the TEmn bit become 1 and start counting.
(4) Thereafter, on the valid edge of the TImn input, the value of the TCRmn register is decremented
by counting the clock.
Figure 5-27 Operation timing (event counter mode)
Remark This is the timing when no noise filter is used. If a noise filter is used, edge detection is delayed by another 2
f
MCK
cycles (3 to 4 cycles total) from the TImn input. The 1-cycle error is due to the fact that the TImn input is out
of sync with the count clock (f
MCK
).
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