CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4)
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Figure 5-45 Operation procedure for interval timer/square wave output function
The input clock of the timer unit m is in a stopped
supply state.
(stop providing clock, cannot write registers)
Set the TM4mEN bit of peripheral enable register 0
(PER0) to 1.
The input clock of the timer unit m is in a supplied
state.
(Start providing clock capable of writing registers)
Set timer clock selection register m (TPSm).
Determine the clock frequency for CKm0 ~ CKm3.
Set timer mode register mn (TMRmm) (determine the
channel operation mode).
The timer data register mn (TDRmn) is set with interval
(period) value.
The channel is in an operational stop state.
(Provide clocks, consume a portion of the Power)
Using TOmn output:
Set the TOMmn bit of the timer output mode register m
(TOMm) to 0 (master channel output mode).
Set the TOLmn bit to 0.
Set the TOmn bit to determine the initial level of the
TOmn output.
Set TOEmn bit to 1 to enable TOmn output.
Set the port register and port mode register to 0.
The TOmn pin is in the Hi-Z output state.
When the port mode register is in output mode and
the port register is 0, the initially set level of the
TOmn is output.
The TOmn is unchanged because the channel is in
an operational stop state.
The TOmn pin outputs the level set by the TOmn.
(Set TOEmn bit to 1 only when using TOmn output
and restarting)
Set TSmn (TSHm1, TSHm3) to 1.
Automatically returned to '0' because the TSmn
(TSHm1, TSHm3) bit is a trigger bit.
The TEmn (TEHm1, THEm3) bit becomes 1 and
starts counting.
Load the value of the TDRmn register into the timer
count register mn (TCRmn). When the MDmn 0 bit
of the TMRmn register is '1', INTTMmn is generated
and TOmn is output alternately.
You can change the setting values of the TDRmn
register at will.
It can read TCRmn register at any time.
TSRmn register cannot be used.
It can change the TOm register and TOEm register
settings.
Prevents the setting of the TMRmn register, TOMmn
bit, and TOLmn bit from being changed.
The counter (TCRmn) counts down. If the count
goes to 0000H, the value of the TDRmn register is
loaded again into the TCRmn register and counting
continues. When TCRmn is detected as 0000H,
INTTMmn is generated and TOmn is output
interleaved. This run is repeated thereafter.
Set TTmn (TTHm1, TTHm3) to 1.
Automatically returned to '0' because the TTmn
(TTHm1, TTHm3) bit is a trigger bit.
The TEmn (TEHm1, TEHmn) bit changes to 0 and
stops counting.
The TCRmn register maintains count values and
stops counting.
The TOmn output is not initialized and remains in
state.
Set the TOEmn bit to 0 and set the TOmn bit.
The TOmn pin outputs the level set by the TOmn
bit.
To maintain the TOmn pin output level:
Set the TOmn to 0 after setting the value to be
maintained for the port register.
The TOmn pin output level does not need to be
maintained: No settings are required.
Maintain the output level of the TOmn pin through
port functionality.
Set the TM4mEN of the PER0 register to 0.
The input clock of the timer unit m is in a stopped
supply state.
Initialize the SFRs of all circuits and channels.
(TOmn bit becomes 0 and TOmn pin becomes
port function)
Remarks m: Unit number (m= 0,1) n: channel number (n=0 ~ 3).
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