Cmsemicon CMS32L051 - Page 186

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CMS32L051 User Manual |Chapter 5 Universal Timer Unit (Timer4)
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Figure 5-63 Example of register settings for single-trigger pulse output function (master channel)
(a) Timer mode register mn (TMRmn).
CKSmn1
1/0
CKSmn0
0
0
CCSmn
0
MAS
TERmn
Note
1
STSmn2
0
STSmn1
0
STSmn0
1
CISmn1
1/0
CISmn0
1/0
0 0
MDmn3
1
MDmn2
0
MDmn1
0
MDmn0
0
14 13 12 11 10 9 8 7 6 5 4 3 2 1 015
TMRmn
operation mode of Channel N
100B: single counting mode
start trigger during operation
0: Trigger input invalid.
start trigger selection
001B: Select Timn pin input valid edge
MASTERmn bit configuration (Channel 2)
1: master control channel
counting clock selection
0: Select operational clock (fMCK)
operational clock (fMCK) selection
00B: select CKm0 as operational clock of Channel n
10B: select CKm1 as operational clock of Channel n.
TImn Pin input edge selection
00B: Detect falling edge
01B: Detect rising edge
10B: Detect both edges
11B: reserved
(b) Timer output register m (TOm).
bit n
TOm
TOmn
0
0: Output 0 by TOmn.
(c) The timer output enable register m (TOEm).
bit n
TOEm
TOEmn
0
0: Stop TOmn output by the count
run.
(d) Timer output level register m (TOLm).
bit n
TOLm
TOLmn
0
0: 0 is set at TOMmn=0 (master channel
output mode).
(e) Timer outputs mode register m (TOMm).
bit n
TOMm
TOMmn
0
0: Set the master channel output mode.
concentrate
TMRm2
: MASTERmn=1
TMRm0
: Fixed to 0.
Note m: Unit number (m= 0,1) n: master channel number (n=0, 2).