Cmsemicon CMS32L051 - Page 300

V1.2.2
CMS32L051 User Manual |Chapter 12 Universal Serial Communication Unit
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A block diagram of universal serial communication unit 0 is shown in Figure 12-1.
Figure 12-1 Diagram of universal serial communication unit 0
peripherial enable
register0 (PER0)
SCI0EN
serial clock selection register0
(SPS0)
serial output register (SO0)
serail output voltage regsiter0 (SOL0)
serial output enable register0 (SOE0)
noise filter enable
regsiter 0 (NFEN0)
pre-scaler
selector selector
fCLK
fCLK/2
0
~fCLK/2
15
fCLK/2
0
~fCLK/2
15
channel0
(support LIN-
bus)
CK01
CK00
fSCK
选择器
选择器
serial data register00 (SDR00)
(Clock frequency division
configuration portion)
(Buffer register portion)
clock control
circuit
shift register
syncrh
onizati
on
circuit
edge
detecti
on
syncrh
onizati
on
circuit
whether
allows
noise
removal
edge /
voltage
detection
edge
detection
serial data register00 (SDR00)
input switch control register (ISC)
When UART0
slave selection input
pin
(SSPI00时：SS00)
serial data input
pins
(SSPI00：SDI00)
(IIC00：SDA00)
(UART0：RxD0)
PMxx
output
latch (Pxx)
SSIE00
SNFEN00
serial communication operation
configuration register00 (SCR00)
serial status register00
(SSR00)
error
message
Clean up
error
control
circuit
interrupt control
circuit
output control
circuit
output
latch (Pxx)
PMxx
serial data output pin
(SSPI00：SDO00)
(IIC00：SDA00)
(UART0：TxD0)
serial transmission completion interrupt
(SSPI00：INTSSPI00)
(IIC00：INTIIC00)
(UART0：INTST0)
mode selection
SSPI00 or IIC00 or
UART0 (used as
transmission)
communication
control circuit
serail flag clean trigger
register00 (SIR00)
fMC
K
When SSPI00：
SCLK00)
(when IIC00：
SCL00)
serial clock input/output
pin
SSPI01：SCLK01)
(IIC01：SCL01)
serial clock input/output
pin
channel1
(support LIN-
bus)
serial data input
pins(SSPI01：
SDI01)
(IIC01：SDA01)
SSPI10 ：SCLK10)
(IIC10：SCL10)
serial clock input/output
pin
serial data Input pins
(SSPI10：SDI10)
(IIC10：SDA10)
(UART0：RxD1)
SSPI11：SCLK11)
(IIC11：SCL11)
serial clock input/output pin
serial data Input
pins(SSPI11：SDI11)
(IIC11：SDA11)
Channel 2
Channel 3
syncr
honiz
ation
circuit
选择
器
edge / voltage
detection
CK01
CK00
CK01 CK00
CK00
CK01
syncr
honiz
ation
circuit
edge / voltage
detection
edge / voltage
detection
syncr
honiz
ation
circuit
selector
whether
allows
noise
removal
SNFEN10
communication
control circuit
mode selection
SSPI00 or IIC00 or
UART0 (used as
receiption)
communication
control circuit
mode selection
SSPI11 or IIC11
or
UART1(used as
receiption)
mode
selectionSSPI10 or
IIC10 or
UART1(used as
transmission)
communication
control circuit
error
control
circuit
serial data output pin
(SSPI01：SDO01)
(IIC01：SDA01)
serial transmission completion interrupt
(SSPI01：INTSSPI01)
(IIC01：INTIIC01)
(UART1：INTSR0)
serial transmission error interrupt
(INTSRE0)
serial data output pin
(SSPI10：SDO10)
(IIC10：SDA10)
(UART1：TxD1)
serial transmission completion interrupt
(SSPI10：INTSSPI10)
(IIC10：INTIIC10)
(UART1：INTST1)
serial data output pin
(SSPI11：SDO11)
(IIC11：SDA11)
serial transmission completion interrupt
(SSPI11：INTSSPI11)
(IIC11：INTIIC11)
(UART1：INTSR1)
serial transmission error interrupt
(INTSRE1)
error
control
circuit
UART1时
serial channel enable
status register0 (SE0)
serial channel start
register0 (SS0)
serial channel stop register0 (ST0)
selector
selector
selector
communication status