CMS32L051 User Manual |Chapter 14 Serial interface IICA
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(9) Ack generation circuit, stop condition detection circuit, start condition detection circuit, Ack detection
circuit
These circuits generate and detect various states.
(10) Data hold time correction circuit
This circuit generates a data hold time for the serial clock to fall.
(11) Start condition generation circuit
If the STTn bit is 1, this circuit generates a start condition.
However, in a state where scheduled communication is disabled (IICRSVn bit=1) and the bus is not
released (IICBSYnbit=1), the start condition request is ignored and the STCFn bit is 1 .
(12) Stop condition generation circuit
If the SPTn bit is 1, this circuit generates a stop condition.
(13) Bus status detection circuitry
This circuit detects whether the bus is released by detecting the start and stop conditions. However, the
bus state cannot be detected immediately during operation, so the initial state of the bus state detection circuit
must be set via the STCENn bit.
Remark 1.STTn bit: bit1 of IICA control register n0 (IICCTLn0).
SPTn bit: bit0 of IICA control register n0 (IICCTLn0).
IICRSVn bit: bit0 of IICA flag register n (IICFn).
IICBSYn bit: Bit6 of IICA flag register n (IICFn).
STCFn bit: bit7 of IICA flag register n (IICFn).
STCENn bit: bit1 of IICA flag register n (IICFn).
2. n=0
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