CMS32L051 User Manual |Chapter 14 Serial interface IICA
www.mcu.com.cn 490 / 703
Figure 14-6 Format of IICA control register n0 (IICCTLn0) (4/4)
Considerations for setting timing:
Disables this bit setting to "1" during transmission. This bit can only be set to "1" during
the waiting period when ACKEn is at "0" and notifying the slave that receiving it has completed.
Master Send: During the Ack, the stop condition may not be generated properly. This bit must be set to
"1" during the wait period after the 9th clock is output.
1 at the same time as the trigger of the start condition (STTn).
SPTn can only be set to "1" in the case of the master device.
When the WTIMn bit is "0", it must be noted that if the SPTn bit is set to "1" during the wait after 8 clocks
of output, the stop condition is generated during the high level of the 9th clock after the release of the
wait. The WTIMn bit must be set from "0" to "1" during the wait period after 8 clocks of output and the
SPTn bit must be set to "1" during the wait period after the 9th clock of output.
After setting the SPTn to "1", it is forbidden to set this bit "1" again until the clear condition is met.
fails
detected.
LRELn bit being 1 (exit
communication).
the IICEn bit is 0 (stop running).
Note Read value of the SPTn bit is always 0.
Notice When bit 3 (TRCn) of the IICA status register n (IICSn) is "1" (transmit status) and if bit 5 (WRELn) of the IICCTLn0
register is set to "1" at the 9th clock to release the wait, the SDAAn line is set to high impedance after clearing the
TRCn bit (receive state). The wait must be released by writing "1" to the TRCn bit of the IICA shift register n
(transmit status).
Remark n=0
To Next Page
Loading...