CMS32L051 User Manual |Chapter 14 Serial interface IICA
www.mcu.com.cn 489 / 703
Figure 14-6 Format of IICA control register n0 (IICCTLn0) (3/4)
The trigger of the start condition
Start conditions are not generated.
When the bus is released (standby, IICBSYn bit is 0): If this
bit is 1, a start condition is generated (as the start of the
master device). While a third party is communicating:
Used as a starting condition reservation sign. If this bit is 1, the start condition is
automatically generated after the bus is released.
Even if this bit 1 is removed, the STTn bit is cleared and the STTn clear flag (STCFn) is
set to 1 without generating a start condition. Wait Status (Master Device):
A restart condition is generated after the wait is released.
Considerations for set timing:
Disables this bit to "1" during transmission. This bit "1" can only be placed during the
waiting period when ACKEn is "0" and notifying the slave that receiving it has completed.
Master Send: During the reply, the start condition may not be generated normally. This bit 1 must be
placed during the waiting period after the 9th clock is output.
1 at the same time as the trigger of the stop condition (SPTn).
STTn to 1, it is forbidden to put this bit 1 again until the Clear condition is met.
Clear condition (STTn=0).
Set STTn to 1 in a state where communication
reservation is prohibited.
In the event of a failed arbitration
Master device generates start conditions.
LRELn bit being 1 (exit
communication).
the IICEn bit is 0 (stop running).
Note 1. In the state where the IICEn bit is 0, the signal for this bit is invalid.
2. The read value of the STTn bit is always 0.
Note 1 If bit1 (STTn) is read after setting the data, this bit becomes 0.
2. IICRSVn: bit0 of the IICA flag register n (IICFn).
STCFn: Bit7 of the IICA flag register n (IICFn).
3.n=0
To Next Page
Loading...