CMS32L051 User Manual |Chapter 14 Serial interface IICA
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Figure 14-6 Format of IICA control register n0 (IICCTLn0) (2/4)
Enable or disable interrupt requests generated by stop condition detection
When the WUPn bit of IICA control register n1 (IICCTLn1) is 1, even if the SPIEn is 1 It also does not
produce a stop condition interrupt.
Clear condition (SPIEn=0).
Wait for and interrupt the control of the request
An interrupt request signal is generated on the falling edge of the 8th clock.
Master device: After 8 clocks are output, set the clock output to low and wait.
Slave: After entering 8 clocks, set the clock low and wait for the master device.
An interrupt request signal is generated on the falling edge of the 9th clock.
Main device: After 9 clocks are output, set the clock output to low and wait.
Slave: After entering 9 clocks, set the clock low and wait for the master device.
During address transfer, regardless of the setting of this bit, an interrupt occurs on the falling edge of the
9th clock; After the end of the address transfer, this bit is set
Effect. The master device enters the wait state on the 9th clock falling edge during address transmission.
The slave device that receives the address of the local station is generating an answer
The descending edge of the 9th clock (ACK) enters the waiting state, but the slave device that receives
the expansion code enters the waiting state on the 8th clock falling edge.
Clear condition (WTIMn=0).
Allow answers. Set the SDAAn line low during the 9th clock.
Clear condition (ACKEn=0).
Note 1 In the state where the IICEn bit is 0, the signal for this bit is invalid. This bit must be set during this time.
2. When the extension code is not in the address transmission process, the config valueis invalid. When a slave
device and the address matches, an answer is generated regardless of the config value.
Remark n=0
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