CMS32L051 User Manual |Chapter 21 Reset Function
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Reset timing
When low is input to the RESETB pin, a reset is generated. Then, if RESETB is quoted high, the reset
state is released, and execution begins with a high-speed internal oscillator clock after the reset process is
complete.
Figure 21-2 Timing of the RESETB input
high speed internal
osc clock
high speed system
clock (select X1 osc
scenario)
CPU status
RESETB pin
internal reset signal
normal
operation
reset period
wait till osc precision stablized
start X1 oscilation via software configuration
normal operation
(high speed internal osc clock)
delay
reset processing time while
releasing external reset
Port in
Hi-Z
Note3
Note2
For resets caused by watchdog timer overflow, system reset request bit assertion, RAM parity error
detection, or detection of illegal memory access, the reset state is automatically released and execution
begins with a high-speed internal oscillator clock after the reset process is completed.
Figure 21-3 Reset timing due to overflow of watchdog timer, set of system reset request bits, detection of
RAM parity errors, or detection of illegal memory access
watchdog timer overflow/
system reset request bit set /
RAM parity error check detection/
illegal register storage detection
internal reset signal
normal
operation
reset period (osc
stop)
wait till osc precision stablized
start X1 oscilation via software
configuration
normal operation (high speed internal
osc clock)
Hi-Z
reset
processing
0.0511ms(TYP.),
0.0701ms(MAX.)
high speed internal osc
clock
high speed system clock
(select X1 osc scenario)
CPU status
Port in
Note3
Note 1 Port pins P10, P26, P40, P137 become the following states:
High impedance during external reset or POR reset.
(internal pull-up resistor is connected).
Note that the watchdog timer is no exception, resetting when an internal reset occurs.
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