RM0390 Rev 4 1119/1328
RM0390 USB on-the-go full-speed/high-speed (OTG_FS/OTG_HS)
1264
Bit 25 ULPIIPD: ULPI interface protect disable for USB OTG HS
This bit controls the circuitry built in the PHY to protect the ULPI interface when the link tri-
states stp and data. Any pull-up or pull-down resistors employed by this feature can be
disabled. Refer to the ULPI specification for more details.
0: Enables the interface protection circuit
1: Disables the interface protection circuit
Bit 24 PTCI: Indicator pass through for USB OTG HS
This bit controls whether the complement output is qualified with the internal V
BUS
valid
comparator before being used in the V
BUS
state in the RX CMD. Refer to the ULPI
specification for more details.
0: Complement Output signal is qualified with the Internal V
BUS
valid comparator
1: Complement Output signal is not qualified with the Internal V
BUS
valid comparator
Bit 23 PCCI: Indicator complement for USB OTG HS
This bit controls the PHY to invert the ExternalVbusIndicator input signal, and generate the
complement output. Refer to the ULPI specification for more details.
0: PHY does not invert the ExternalVbusIndicator signal
1: PHY inverts ExternalVbusIndicator signal
Bit 22 TSDPS: TermSel DLine pulsing selection for USB OTG HS
This bit selects utmi_termselect to drive the data line pulse during SRP (session request
protocol).
0: Data line pulsing using utmi_txvalid (default)
1: Data line pulsing using utmi_termsel
Bit 21 ULPIEVBUSI: ULPI external V
BUS
indicator for USB OTG HS
This bit indicates to the ULPI PHY to use an external V
BUS
overcurrent indicator.
0: PHY uses an internal V
BUS
valid comparator
1: PHY uses an external V
BUS
valid comparator
Bit 20 ULPIEVBUSD: ULPI External V
BUS
Drive for USB OTG HS
This bit selects between internal or external supply to drive 5 V on V
BUS
, in the ULPI PHY.
0: PHY drives V
BUS
using internal charge pump (default)
1: PHY drives V
BUS
using external supply.
Bit 19 ULPICSM: ULPI clock SuspendM for USB OTG HS
This bit sets the ClockSuspendM bit in the interface control register on the ULPI PHY. This bit
applies only in the serial and carkit modes.
0: PHY powers down the internal clock during suspend
1: PHY does not power down the internal clock
Bit 18 ULPIAR: ULPI Auto-resume for USB OTG HS
This bit sets the AutoResume bit in the interface control register on the ULPI PHY.
0: PHY does not use AutoResume feature
1: PHY uses AutoResume feature
Bit 17 ULPIFSLS: ULPI FS/LS select for USB OTG HS
The application uses this bit to select the FS/LS serial interface for the ULPI PHY. This bit is
valid only when the FS serial transceiver is selected on the ULPI PHY.
0: ULPI interface
1: ULPI FS/LS serial interface
Bit 16 Reserved, must be kept at reset value.
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