RM0390 Rev 4 285/1328
RM0390 Flexible memory controller (FMC)
324
Figure 51. Synchronous multiplexed write mode waveforms - PSRAM (CRAM)
1. The memory must issue NWAIT signal one cycle in advance, accordingly WAITCFG must be programmed to 0.
2. Byte Lane (NBL) outputs are not shown, they are held low while NEx is active.
!DDR;= DATA
ADDR;=
-EMORYTRANSACTIONBURSTOFHALFWORDS
(#,+
#,+
!;=
.%X
./%
.7%
(I:
.!$6
.7!)4
7!)4#&'
!$;=
CLOCK CLOCK
$!4,!4
INSERTEDWAITSTATE
AIF
#,+CYCLES
DATA
Table 72. FMC_BCRx bit fields
Bit number Bit name Value to set
31-22 Reserved 0x000
21 WFDIS As needed
20 CCLKEN As needed
19 CBURSTRW 0x1
18:16 CPSIZE As needed (0x1 for CRAM 1.5)
15 ASYNCWAIT 0x0
14 EXTMOD 0x0
13 WAITEN
To be set to 1 if the memory supports this feature, to be kept at 0
otherwise.
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