RM0390 Rev 4 209/1328
RM0390 Direct memory access controller (DMA)
237
When the data width (programmed in the PSIZE or MSIZE bits in the DMA_SxCR register)
is a half-word or a word, respectively, the peripheral or memory address written into the
DMA_SxPAR or DMA_SxM0AR/M1AR registers has to be aligned on a word or half-word
address boundary, respectively.
Peripheral-to-memory mode
Figure 26 describes this mode.
When this mode is enabled (by setting the bit EN in the DMA_SxCR register), each time a
peripheral request occurs, the stream initiates a transfer from the source to fill the FIFO.
When the threshold level of the FIFO is reached, the contents of the FIFO are drained and
stored into the destination.
The transfer stops once the DMA_SxNDTR register reaches zero, when the peripheral
requests the end of transfers (in case of a peripheral flow controller) or when the EN bit in
the DMA_SxCR register is cleared by software.
In direct mode (when the DMDIS value in the DMA_SxFCR register is ‘0’), the threshold
level of the FIFO is not used: after each single data transfer from the peripheral to the FIFO,
the corresponding data are immediately drained and stored into the destination.
The stream has access to the AHB source or destination port only if the arbitration of the
corresponding stream is won. This arbitration is performed using the priority defined for
each stream using the PL[1:0] bits in the DMA_SxCR register.
Figure 26. Peripheral-to-memory mode
1. For double-buffer mode.
Memory-to-peripheral mode
Figure 27 describes this mode.
When this mode is enabled (by setting the EN bit in the DMA_SxCR register), the stream
immediately initiates transfers from the source to entirely fill the FIFO.
-EMORYBUS
0ERIPHERALBUS
2%1?342%!-X
!RBITER
$-!?3X-!2
&)&/
!("MEMORY
PORT
!("PERIPHERAL
PORT
$-!?3X0!2
&)&/
LEVEL
$-!CONTROLLER
$-!?3X-!2
DESTINATION
SOURCE
PERIPHERAL
-EMORY
0ERIPHERAL$-!REQUEST
AI
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