Reset and clock control (RCC) RM0390
158/1328 RM0390 Rev 4
6.3.19 RCC APB2 peripheral clock enabled in low power mode register
(RCC_APB2LPENR)
Address offset: 0x64
Reset value: 0x0x00C7 FF33
Access: no wait state, word, half-word and byte access.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res.
SAI2
LPEN
SAI1
LPEN
Res. Res. Res.
TIM11
LPEN
TIM10
LPEN
TIM9
LPEN
rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res.
SYSCFG
LPEN
SPI4
LPEN
SPI1
LPEN
SDIO
LPEN
ADC3
LPEN
ADC2
LPEN
ADC1
LPEN
Res. Res.
USART6
LPEN
USART1
LPEN
Res. Res.
TIM8
LPEN
TIM1
LPEN
rw rw rw rw rw rw rw rw rw rw rw
Bits 31:24 Reserved, must be kept at reset value.
Bit 23 SAI2LPEN: SAI2 clock enable during Sleep mode
This bit is set and cleared by software.
0: SAI2 clock disabled during Sleep mode
1: SAI2 clock enabled during Sleep mode
Bit 22 SAI1LPEN: SAI1 clock enable during Sleep mode
This bit is set and cleared by software.
0: SAI1 clock disabled during Sleep mode
1: SAI1 clock enabled during Sleep mode
Bits 21:19 Reserved, must be kept at reset value.
Bit 18 TIM11LPEN: TIM11 clock enable during Sleep mode
This bit is set and cleared by software.
0: TIM11 clock disabled during Sleep mode
1: TIM11 clock enabled during Sleep mode
Bit 17 TIM10LPEN: TIM10 clock enable during Sleep mode
This bit is set and cleared by software.
0: TIM10 clock disabled during Sleep mode
1: TIM10 clock enabled during Sleep mode
Bit 16 TIM9LPEN: TIM9 clock enable during sleep mode
This bit is set and cleared by software.
0: TIM9 clock disabled during Sleep mode
1: TIM9 clock enabled during Sleep mode
Bit 15 Reserved, must be kept at reset value.
Bit 14 SYSCFGLPEN: System configuration controller clock enable during Sleep mode
This bit is set and cleared by software.
0: System configuration controller clock disabled during Sleep mode
1: System configuration controller clock enabled during Sleep mode
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