USB on-the-go full-speed/high-speed (OTG_FS/OTG_HS) RM0390
1168/1328 RM0390 Rev 4
31.15.41 OTG device threshold control register (OTG_DTHRCTL)
Address offset: 0x0830
Reset value: 0x0000 0000
Note: Configuration register applies only to USB OTG HS
Bits 31:12 Reserved, must be kept at reset value.
Bits 11:0 DVBUSP[11:0]: Device V
BUS
pulsing time. This feature is only relevant to OTG1.3.
Specifies the V
BUS
pulsing time during SRP. This value equals:
V
BUS
pulsing time in PHY clocks / 1 024
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. ARPEN Res. RXTHRLEN[8:0]
RXTH
REN
rw rw rw rw rw rw rw rw rw rw rw
1514131211109876543210
Res. Res. Res. Res. Res. TXTHRLEN[8:0]
ISOT
HREN
NONIS
OTH
REN
rw rw rw rw rw rw rw rw rw rw rw
Bits 31:28 Reserved, must be kept at reset value.
Bit 27 ARPEN: Arbiter parking enable
This bit controls internal DMA arbiter parking for IN endpoints. When thresholding is enabled
and this bit is set to one, then the arbiter parks on the IN endpoint for which there is a token
received on the USB. This is done to avoid getting into underrun conditions. By default
parking is enabled.
Bit 26 Reserved, must be kept at reset value.
Bits 25: 17 RXTHRLEN[8:0]: Receive threshold length
This field specifies the receive thresholding size in 32-bit words. This field also specifies the
amount of data received on the USB before the core can start transmitting on the AHB. The
threshold length has to be at least eight 32-bit words. The recommended value for
RXTHRLEN is to be the same as the programmed AHB burst length (HBSTLEN bit in
OTG_GAHBCFG).
Bit 16 RXTHREN: Receive threshold enable
When this bit is set, the core enables thresholding in the receive direction.
Bits 15: 11 Reserved, must be kept at reset value.
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