ST STM32F446 Series User Manual

RM0390 Rev 4 737/1328
RM0390 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface
758
Figure 270. Bus transfer diagrams for SMBus master receiver
23.4.14 Error conditions
The following are the error conditions which may cause communication to fail.
Bus error (BERR)
A bus error is detected when a START or a STOP condition is detected and is not located
after a multiple of 9 SCL clock pulses. A START or a STOP condition is detected when a
SDA edge occurs while SCL is high.
The bus error flag is set only if the FMPI2C is involved in the transfer as master or
addressed slave (i.e not during the address phase in slave mode).
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ST STM32F446 Series Specifications

General

Brand	ST
Model	STM32F446 Series
Category	Microcontrollers
Language	English