Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0390
756/1328 RM0390 Rev 4
23.7.10 Receive data register (FMPI2C_RXDR)
Address offset: 0x24
Reset value: 0x0000 0000
Access: No wait states
23.7.11 Transmit data register (FMPI2C_TXDR)
Address offset: 0x28
Reset value: 0x0000 0000
Access: No wait states
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. RXDATA[7:0]
r
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 RXDATA[7:0] 8-bit receive data
Data byte received from the I
2
C bus.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. TXDATA[7:0]
rw
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 TXDATA[7:0] 8-bit transmit data
Data byte to be transmitted to the I
2
C bus.
Note: These bits can be written only when TXE=1.
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