RM0390 Rev 4 633/1328
RM0390 Basic timers (TIM6&TIM7)
639
Figure 234. Counter timing diagram, update event when ARPE = 0
(TIMx_ARR not preloaded)
Figure 235. Counter timing diagram, update event when ARPE=1
(TIMx_ARR preloaded)
19.3.3 Clock source
The counter clock is provided by the Internal clock (CK_INT) source.
The CEN (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual
control bits and can be changed only by software (except for UG that remains cleared
automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal
clock CK_INT.
Figure 236 shows the behavior of the control circuit and the upcounter in normal mode,
without prescaler.
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