SPDIF receiver interface (SPDIFRX) RM0390
904/1328 RM0390 Rev 4
27.3.3 SPDIFRX tolerance to clock deviation
The SPDIFRX tolerance to clock deviation depends on the number of sample clock cycles in
one bit slot. The fastest SPDIFRX_CLK is, the more robust the reception will be. The ratio
between SPDIFRX_CLK frequency and the symbol rate must be at least 11.
Two kinds of phenomenon (at least!) can degrade the reception quality:
• The cycle-to-cycle jitter which reflects the difference of transition length between two
consecutive transitions.
• The long term jitter which reflects a cumulative effect of the cycle-to-cycle jitter. It can
be seen as a low-frequency symbol modulation.
27.3.4 SPDIFRX synchronization
The synchronization phase starts when setting SPDIFRXEN to 0b01 or 0b11. Figure 346
shows the synchronization process.
If the bit WFA of SPDIFRX_CR register is set to 1, then the peripheral must first detect
activity on the selected SPDIFRX_IN line before starting the synchronization process. The
activity detection is performed by detecting four transitions on the selected SPDIFRX_IN.
The peripheral remains in this state until transitions are not detected. This function can be
particularly helpful because the IP switches in COARSE SYNC mode only if activity is
present on the selected SPDIFRX_IN input, avoiding synchronization errors. See
Section 27.4: Programming procedures for additional information.
The user can still set the SPDIFRX into STATE_IDLE by setting SPDIFRXEN to 0. If the
WFA is set to 0, the peripheral starts the coarse synchronization without checking activity.
The next step consists on doing a first estimate of the thresholds (COARSE SYNC), in order
to perform the fine synchronization (FINE SYNC). Due to disturbances of the SPDIFRX line,
it could happen that the process is not executed first time right. For this purpose, the user
can program the number of allowed re-tries (NBTR) before setting SERR error flag.
When the SPDIFRX has been able to measure properly the duration of 24 and 40
consecutive symbols then the FINE SYNC is completed, the threshold values are updated,
and the flag SYNCD is set to 1. Refer to Section : Transition coder and preamble detector
for additional information.
Two kinds of errors are detected:
• An overflow of the TRCNT, which generally means that there is no valid S/PDIF stream
in the input line. This overflow is indicated by TERR flag.
• The number of retries reached the programmed value. This means that strong jitter is
present on the S/PDIF signal. This error is indicated by SERR flag.
When the first FINE SYNC is completed, the reception of channel status (C) and user data
(U) will start when the next “B” preamble is detected (see Figure 350).Then the user can
read IEC-60958 C and U bits through SPDIFRX_CSR register. According to this information
the user can then select the proper settings for DRFMT and RXSTEO. For example if the
user detects that the current audio stream transports encoded data, then he can put
RXSTEO to 0, and DRFMT to 0b10 prior to start data reception. Note that DRFMT and
RXSTEO cannot be modified when SPDIFRXEN = 0b11. Writes to these fields are ignored if
SPDIFRXEN is already 0b11, though these field can be changed with the same write
instruction that causes SPDIFRXEN to become 0b11.
Then the SPDIFRX waits for SPDIFRXEN = 0b11 and the “B” preamble before starting
saving audio samples.
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