RM0390 Rev 4 907/1328
RM0390 SPDIF receiver interface (SPDIFRX)
929
Figure 348. SPDIFRX States
When SPDIFRX is in STATE_IDLE:
• The software can transition to STATE_SYNC by setting SPDIFRXEN to 0b01 or 0b11
When SPDIFRX is in STATE_SYNC:
• If the synchronization fails or if the received data are not properly decoded with no
chance of recovery without a re-synchronization (FERR or SERR or TERR = 1), the
SPDIFRX goes to STATE_STOP, and waits for software acknowledge.
• When the synchronization phase is completed, if SPDIFRXEN = 0b01 the peripheral
remains in this state.
• At any time the software can set SPDIFRXEN to 0, then SPDIFRX returns immediately
to STATE_IDLE. If a DMA transfer is on-going, it will be properly completed.
• The SPDIFRX goes to STATE_RCV if SPDIFRXEN = 0b11 and if the SYNCD = 1
When SPDIFRX is in STATE_RCV:
• If the received data are not properly decoded with no chance of recovery without a re-
synchronization (FERR or SERR or TERR = 1), the SPDIFRX goes to STATE_STOP,
and waits for software acknowledge.
• At any time the software can set SPDIFRXEN to 0, then SPDIFRX returns immediately
to STATE_IDLE. If a DMA transfer is on-going, it will properly be completed.
When SPDIFRX is in STATE_STOP:
• The SPDIFRX stops reception and synchronization, and waits for the software to set
the bit SPDIFRXEN to 0, in order to clear the error flags.
67$7(B,'/(
67$7(B6<1&
67$7(B5&9
67$7(B6723
63',)5;(1 E
6:
RU
63',)5;(1 E
6:
63',)5;(1 E6:
DQG
V\QFBGRQH +:
)(55 +:RU
7(55 +:
63',)5;(1 E6:
63',)5;(1 E6:
63',)5;(1 E6:
)(55 +:RU
7(55 +:RU
6(55 +:
127(V\QFBGRQHLVDQLQWHUQDOHYHQWLQIRUPLQJWKDWWKH63',)5;LVSURSHUO\V\QFKURQL]HG
06Y9