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Reset and clock control (RCC) RM0390

142/1328 RM0390 Rev 4

6.3.9 RCC APB2 peripheral reset register (RCC_APB2RSTR)

Address offset: 0x24

Reset value: 0x0000 0000

Access: no wait state, word, half-word and byte access.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res.

SAI2

RST

SAI1

RST

Res. Res. Res.

TIM11

RST

TIM10

RST

TIM9

RST

rw rw rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res.

SYSCFG

RST

SPI4

RST

SPI1

RST

SDIO

RST

Res. Res.

ADC

RST

Res Res

USART6

RST

USART1

RST

Res. Res.

TIM8

RST

TIM1

RST

rw rw rw rw rw rw rw rw rw

Bits 31:24 Reserved, must be kept at reset value.

Bit 23 SAI2RST: SAI2 reset

This bit is set and reset by software.

0: does not reset SAI2

1: resets SAI2

Bit 22 SAI1RST: SAI1 reset

This bit is set and reset by software.

0: does not reset SAI1

1: resets SAI1

Bits 21:19 Reserved, must be kept at reset value.

Bit 18 TIM11RST: TIM11 reset