RM0390 Rev 4 121/1328
RM0390 Reset and clock control (RCC)
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hardware. An interrupt can be generated if enabled in the RCC clock interrupt register
(RCC_CIR).
The HSE Crystal can be switched on and off using the HSEON bit in the RCC clock control
register (RCC_CR).
6.2.2 HSI clock
The HSI clock signal is generated from an internal 16 MHz RC oscillator and can be used
directly as a system clock, or used as PLL input.
The HSI RC oscillator has the advantage of providing a clock source at low cost (no external
components). It also has a faster startup time than the HSE crystal oscillator however, even
with calibration the frequency is less accurate than an external crystal oscillator or ceramic
resonator.
Calibration
RC oscillator frequencies can vary from one chip to another due to manufacturing process
variations, this is why each device is factory calibrated by ST for 1% accuracy at T
A
= 25 °C.
After reset, the factory calibration value is loaded in the HSICAL[7:0] bits in the RCC clock
control register (RCC_CR).
If the application is subject to voltage or temperature variations this may affect the RC
oscillator speed. You can trim the HSI frequency in the application using the HSITRIM[4:0]
bits in the RCC clock control register (RCC_CR).
The HSIRDY flag in the RCC clock control register (RCC_CR) indicates if the HSI RC is
stable or not. At startup, the HSI RC output clock is not released until this bit is set by
hardware.
The HSI RC can be switched on and off using the HSION bit in the RCC clock control
register (RCC_CR).
The HSI signal can also be used as a backup source (Auxiliary clock) if the HSE crystal
oscillator fails. Refer to Section 6.2.7: Clock security system (CSS) on page 123.
6.2.3 PLL configuration
The STM32F446xx devices feature three PLLs:
• A main PLL (PLL) clocked by the HSE or HSI oscillator and featuring three different
output clocks:
– The first output is used to generate the high speed system clock (up to 180 MHz)
– The second output can be used to generate the clock for the USB OTG FS
(48 MHz) or the SDIO (
48 MHz).
– The third output can be used to generate the clock for I2S1 and I2S2 clocks,
SPDIF-Rx clock or the high speed system clock.
• Two dedicated PLLs (PLLI2S and PLLSAI) used to generate an accurate clock to
achieve high-quality audio performance on the I2S and SAIs interfaces. PLLSAI and
PLLI2S are also used to generate SPDIF-Rx clock or the 48 MHz clock for USB OTG
FS and SDIO.
Since the main-PLL configuration parameters cannot be changed once PLL is enabled, it is
recommended to configure PLL before enabling it (selection of the HSI or HSE oscillator as
PLL clock source, and configuration of division factors M, N, P, R and Q).
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