ST STM32F446 Series User Manual

Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0390
740/1328 RM0390 Rev 4
initialized before setting the START bit. The end of transfer is managed with the
NBYTES counter. Refer to Master transmitter on page 716.
• In slave mode:
– With NOSTRETCH=0, when all data are transferred using DMA, the DMA must be
initialized before the address match event, or in ADDR interrupt subroutine, before
clearing ADDR.
– With NOSTRETCH=1, the DMA must be initialized before the address match
event.
• For instances supporting SMBus: the PEC transfer is managed with NBYTES counter.
Refer to SMBus Slave transmitter on page 730 and SMBus Master transmitter on
page 734.
Note: If DMA is used for transmission, the TXIE bit does not need to be enabled.
Reception using DMA
DMA (Direct Memory Access) can be enabled for reception by setting the RXDMAEN bit in
the FMPI2C_CR1 register. Data is loaded from the FMPI2C_RXDR register to an SRAM
area configured using the DMA peripheral (refer to Section 9: Direct memory access
controller (DMA)) whenever the RXNE bit is set. Only the data (including PEC) are
transferred with DMA.
• In master mode, the initialization, the slave address, direction, number of bytes and
START bit are programmed by software. When all data are transferred using DMA, the
DMA must be initialized before setting the START bit. The end of transfer is managed
with the NBYTES counter.
• In slave mode with NOSTRETCH=0, when all data are transferred using DMA, the
DMA must be initialized before the address match event, or in the ADDR interrupt
subroutine, before clearing the ADDR flag.
• If SMBus is supported (see Section 23.3: FMPI2C implementation): the PEC transfer is
managed with the NBYTES counter. Refer to SMBus Slave receiver on page 732 and
SMBus Master receiver on page 736.
Note: If DMA is used for reception, the RXIE bit does not need to be enabled.
23.4.16 Debug mode
When the microcontroller enters debug mode (core halted), the SMBus timeout either
continues to work normally or stops, depending on the DBG_I2Cx_STOP configuration bits
in the DBG module.
23.5 FMPI2C low-power modes
Table 138. Low-power modes
Mode Description
Sleep
No effect
FMPI2C interrupts cause the device to exit the Sleep mode.
Stop The contents of FMPI2C registers are kept.
Standby The FMPI2C peripheral is powered down and must be reinitialized after exiting Standby.

ST STM32F446 Series Specifications

General

Brand	ST
Model	STM32F446 Series
Category	Microcontrollers
Language	English