ST STM32F446 Series User Manual

USB on-the-go full-speed/high-speed (OTG_FS/OTG_HS) RM0390
1172/1328 RM0390 Rev 4
31.15.46 OTG device each OUT endpoint-1 interrupt mask register
(OTG_HS_DOEPEACHMSK1)
Address offset: 0x884
Reset value: 0x0000 0000
This register works with the OTG_DOEPINT1 register to generate a dedicated interrupt
OTG_HS_EP1_OUT for endpoint #1. The OUT endpoint interrupt for a specific status in the
OTG_DOEPINT1 register can be masked by writing into the corresponding bit in this
register. Status bits are masked by default.
Note: Configuration register applies only to USB OTG HS
Bit 2 AHBERRM: AHB error mask
0: Masked interrupt
1: Unmasked interrupt
Bit 1 EPDM: Endpoint disabled interrupt mask
0: Masked interrupt
1: Unmasked interrupt
Bit 0 XFRCM: Transfer completed interrupt mask
0: Masked interrupt
1: Unmasked interrupt
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res.
NYET
MSK
NAK
MSK
BERR
M
Res. Res. Res.
OUT
PKT
ERRM
Res.
B2B
STUPM
Res.
OTEPD
M
STUPM
AHB
ERRM
EPDM
XFRC
M
rw rw rw rw rw rw rw rw rw rw
Bits 31:15 Reserved, must be kept at reset value.
Bit 14 NYETMSK: NYET interrupt mask
0: Masked interrupt
1: Unmasked interrupt
Bit 13 NAKMSK: NAK interrupt mask
0: Masked interrupt
1: Unmasked interrupt
Bit 12 BERRM: Babble error interrupt mask
0: Masked interrupt
1: Unmasked interrupt
Bits 11:10 Reserved, must be kept at reset value.
Bit 9 Reserved, must be kept at reset value.
Bit 8 OUTPKTERRM: Out packet error mask
0: Masked interrupt
1: Unmasked interrupt

ST STM32F446 Series Specifications

General

Brand	ST
Model	STM32F446 Series
Category	Microcontrollers
Language	English