Flexible memory controller (FMC) RM0390
250/1328 RM0390 Rev 4
11 Flexible memory controller (FMC)
The Flexible memory controller (FMC) includes three memory controllers:
• The NOR/PSRAM memory controller
• The NAND memory controller
• The Synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) controller
11.1 FMC main features
The FMC functional block makes the interface with: synchronous and asynchronous static
memories, SDRAM memories, and NAND Flash memory. Its main purposes are:
• to translate AHB transactions into the appropriate external device protocol
• to meet the access time requirements of the external memory devices
All external memories share the addresses, data and control signals with the controller.
Each external device is accessed by means of a unique Chip Select. The FMC performs
only one access at a time to an external device.
The main features of the FMC controller are the following:
• Interface with static-memory mapped devices including:
– Static random access memory (SRAM)
– NOR Flash memory/OneNAND Flash memory
– PSRAM (4 memory banks)
– NAND Flash memory with ECC hardware to check up to 8 Kbytes of data
• Interface with synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) memories
• Interface with parallel LCD modules, supporting Intel 8080 and Motorola 6800 modes.
• Burst mode support for faster access to synchronous devices such as NOR Flash
memory, PSRAM and SDRAM)
• Programmable continuous clock output for asynchronous and synchronous accesses
• 8-,16-bit wide data bus
• Independent Chip Select control for each memory bank
• Independent configuration for each memory bank
• Write enable and byte lane select outputs for use with PSRAM, SRAM and SDRAM
devices
• External asynchronous wait control
• Write FIFO with 16 x32-bit depth
• Cacheable Read FIFO with 6 x32-bit depth (6 x14-bit address tag) for SDRAM
controller.
The Write FIFO is common to all memory controllers and consists of:
• a Write Data FIFO which stores the AHB data to be written to the memory (up to 32
bits) plus one bit for the AHB transfer (burst or not sequential mode)
• a Write Address FIFO which stores the AHB address (up to 28 bits) plus the AHB data
size (up to 2 bits). When operating in burst mode, only the start address is stored
except when crossing a page boundary (for PSRAM and SDRAM). In this case, the
AHB burst is broken into two FIFO entries.
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