ST STM32F446 Series User Manual

USB on-the-go full-speed/high-speed (OTG_FS/OTG_HS) RM0390
1124/1328 RM0390 Rev 4
31.15.6 OTG core interrupt register (OTG_GINTSTS)
Address offset: 0x014
Reset value: 0x1400 0020
This register interrupts the application for system-level events in the current mode (device
mode or host mode).
Some of the bits in this register are valid only in host mode, while others are valid in device
mode only. This register also indicates the current mode. To clear the interrupt status bits of
the rc_w1 type, the application must write 1 into the bit.
The FIFO status interrupts are read-only; once software reads from or writes to the FIFO
while servicing these interrupts, FIFO interrupt conditions are cleared automatically.
The application must clear the OTG_GINTSTS register at initialization before unmasking
the interrupt bit to avoid any interrupts generated prior to initialization.
Note: Configuration register for USB OTG FS
Note: Configuration register for USB OTG HS
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WKUP
INT
SRQ
INT
DISC
INT
CIDS
CHG
LPM
INT
PTXFE HCINT
HPRT
INT
RST
DET
Res.
IPXFR/
IN
COMP
ISO
OUT
IISOI
XFR
OEP
INT
IEPINT Res. Res.
rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 r r r rc_w1 rc_w1 rc_w1 r r
1514131211109876543210
EOPF
ISOO
DRP
ENUM
DNE
USB
RST
USB
SUSP
ESUSP Res. Res.
GO
NAK
EFF
GI
NAK
EFF
NPTXF
E
RXF
LVL
SOF
OTG
INT
MMIS CMOD
rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 r r r r rc_w1 r rc_w1 r
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WKUP
INT
SRQ
INT
DISC
INT
CIDS
CHG
Res. PTXFE HCINT
HPRT
INT
Res.
DATAF
SUSP
IPXFR/
IN
COMP
ISO
OUT
IISOI
XFR
OEP
INT
IEPINT Res. Res.
rc_w1 rc_w1 rc_w1 rc_w1 r r r rc_w1 rc_w1 rc_w1 r r
1514131211109876543210
EOPF
ISOO
DRP
ENUM
DNE
USB
RST
USB
SUSP
ESUSP Res. Res.
GO
NAK
EFF
GI
NAK
EFF
NPTXF
E
RXF
LVL
SOF
OTG
INT
MMIS CMOD
rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 r r r r rc_w1 r rc_w1 r

ST STM32F446 Series Specifications

General

Brand	ST
Model	STM32F446 Series
Category	Microcontrollers
Language	English