RM0390 Rev 4 649/1328
RM0390 Window watchdog (WWDG)
652
As an example, let us assume APB1 frequency is equal to 24 MHz, WDGTB[1:0] is set to 3
and T[5:0] is set to 63:
Refer to the datasheets for the minimum and maximum values of the t
WWDG.
21.5 Debug mode
When the microcontroller enters debug mode (Cortex
®
-M4 with FPU core halted), the
WWDG counter either continues to work normally or stops, depending on
DBG_WWDG_STOP configuration bit in DBG module. For more details, refer to
Section 33.16.2: Debug support for timers, watchdog, bxCAN and I2C.
t
WWDG
1 24000⁄ 4096× 2
3
× 63 1+()× 21.85 ms==
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