Flexible memory controller (FMC) RM0390
258/1328 RM0390 Rev 4
11.5 NOR Flash/PSRAM controller
The FMC generates the appropriate signal timings to drive the following types of memories:
• Asynchronous SRAM and ROM
–8 bits
– 16 bits
• PSRAM (CellularRAM™)
– Asynchronous mode
– Burst mode for synchronous accesses
– Multiplexed or non-multiplexed
• NOR Flash memory
– Asynchronous mode
– Burst mode for synchronous accesses
– Multiplexed or non-multiplexed
The FMC outputs a unique Chip Select signal, NE[4:1], per bank. All the other signals
(addresses, data and control) are shared.
Table 47. SDRAM address mapping with 16-bit data bus width
(1)(2)
Row size
Configuration
HADDR(AHB address Lines)
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
11-bit row size
configuration
Res.
Bank
[1:0]
Row[10:0] Column[7:0] BM0
(3)
Res.
Bank
[1:0]
Row[10:0] Column[8:0] BM0
Res.
Bank
[1:0]
Row[10:0] Column[9:0] BM0
Res.
Bank
[1:0]
Row[10:0] Column[10:0] BM0
12-bit row size
configuration
Res.
Bank
[1:0]
Row[11:0] Column[7:0] BM0
Res.
Bank
[1:0]
Row[11:0] Column[8:0] BM0
Res.
Bank
[1:0]
Row[11:0] Column[9:0] BM0
Res.
Bank
[1:0]
Row[11:0] Column[10:0] BM0
13-bit row size
configuration
Res.
Bank
[1:0]
Row[12:0] Column[7:0] BM0
Res.
Bank
[1:0]
Row[12:0] Column[8:0] BM0
Res.
Bank
[1:0]
Row[12:0] Column[9:0] BM0
Re
s.
Bank
[1:0]
Row[12:0] Column[10:0] BM0
1. BANK[1:0] are the Bank Address BA[1:0]. When only 2 internal banks are used, BA1 must always be set to ‘0’.
2. Access to Reserved space (Res.) generates an AHB error.
3. BM0: is the byte mask for 16-bit access.
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