RM0390 Rev 4 53/1328
RM0390 Memory and bus architecture
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2 Memory and bus architecture
2.1 System architecture
In STM32F446xx, the main system consists of 32-bit multilayer AHB bus matrix that
interconnects:
• Seven masters:
–Cortex
®
-M4 with FPU core I-bus, D-bus and S-bus
– DMA1 memory bus
– DMA2 memory bus
– DMA2 peripheral bus
– USB OTG HS DMA bus
• Seven slaves:
– Internal Flash memory ICode bus
– Internal Flash memory DCode bus
– Main internal SRAM1 (112 KB)
– Auxiliary internal SRAM2 (16 KB)
– AHB1 peripherals including AHB to APB bridges and APB peripherals
– AHB2 peripherals
– FMC / QUADSPI
The bus matrix provides access from a master to a slave, enabling concurrent access and
efficient operation even when several high-speed peripherals work simultaneously. This
architecture is shown in Figure 1.
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