RM0390 Rev 4 223/1328
RM0390 Direct memory access controller (DMA)
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9.4 DMA interrupts
For each DMA stream, an interrupt can be produced on the following events:
• Half-transfer reached
• Transfer complete
• Transfer error
• FIFO error (overrun, underrun or FIFO level error)
• Direct mode error
Separate interrupt enable control bits are available for flexibility as shown in Table 36.
Note: Before setting an enable control bit EN = 1, the corresponding event flag must be cleared,
otherwise an interrupt is immediately generated.
Table 36. DMA interrupt requests
Interrupt event Event flag Enable control bit
Half-transfer HTIF HTIE
Transfer complete TCIF TCIE
Transfer error TEIF TEIE
FIFO overrun/underrun FEIF FEIE
Direct mode error DMEIF DMEIE
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